SAM3XA USART2

Universal Synchronous Asynchronous Receiver Transmitter (USART2) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x400A0000	Control Register	USART2_CR	write-only	-
0x400A0004	Mode Register	USART2_MR	read-write	-
0x400A0008	Interrupt Enable Register	USART2_IER	write-only	-
0x400A000C	Interrupt Disable Register	USART2_IDR	write-only	-
0x400A0010	Interrupt Mask Register	USART2_IMR	read-only	0x00000000
0x400A0014	Channel Status Register	USART2_CSR	read-only	-
0x400A0018	Receiver Holding Register	USART2_RHR	read-only	0x00000000
0x400A001C	Transmitter Holding Register	USART2_THR	write-only	-
0x400A0020	Baud Rate Generator Register	USART2_BRGR	read-write	0x00000000
0x400A0024	Receiver Time-out Register	USART2_RTOR	read-write	0x00000000
0x400A0028	Transmitter Timeguard Register	USART2_TTGR	read-write	0x00000000
0x400A0040	FI DI Ratio Register	USART2_FIDI	read-write	0x00000174
0x400A0044	Number of Errors Register	USART2_NER	read-only	-
0x400A004C	IrDA Filter Register	USART2_IF	read-write	0x00000000
0x400A0050	Manchester Encoder Decoder Register	USART2_MAN	read-write	0x30011004
0x400A0054	LIN Mode Register	USART2_LINMR	read-write	0x00000000
0x400A0058	LIN Identifier Register	USART2_LINIR	read-write	0x00000000
0x400A00E4	Write Protect Mode Register	USART2_WPMR	read-write	0x00000000
0x400A00E8	Write Protect Status Register	USART2_WPSR	read-only	0x00000000
0x400A0100	Receive Pointer Register	USART2_RPR	read-write	0x00000000
0x400A0104	Receive Counter Register	USART2_RCR	read-write	0x00000000
0x400A0108	Transmit Pointer Register	USART2_TPR	read-write	0x00000000
0x400A010C	Transmit Counter Register	USART2_TCR	read-write	0x00000000
0x400A0110	Receive Next Pointer Register	USART2_RNPR	read-write	0x00000000
0x400A0114	Receive Next Counter Register	USART2_RNCR	read-write	0x00000000
0x400A0118	Transmit Next Pointer Register	USART2_TNPR	read-write	0x00000000
0x400A011C	Transmit Next Counter Register	USART2_TNCR	read-write	0x00000000
0x400A0120	Transfer Control Register	USART2_PTCR	write-only	0x00000000
0x400A0124	Transfer Status Register	USART2_PTSR	read-only	0x00000000

Register Fields

USART2 Control Register

Name: USART2_CR

Access: write-only

Address: 0x400A0000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	LINWKUP	LINABT	RTSDIS	RTSEN	-	-
15	14	13	12	11	10	9	8
RETTO	RSTNACK	RSTIT	SENDA	STTTO	STPBRK	STTBRK	RSTSTA
7	6	5	4	3	2	1	0
TXDIS	TXEN	RXDIS	RXEN	RSTTX	RSTRX	-	-

• RSTRX: Reset Receiver

  Value	Name	Description
  0	-	No effect.
  1	-	Resets the receiver.

• RSTTX: Reset Transmitter

  Value	Name	Description
  0	-	No effect.
  1	-	Resets the transmitter.

• RXEN: Receiver Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the receiver, if RXDIS is 0.

• RXDIS: Receiver Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the receiver.

• TXEN: Transmitter Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the transmitter if TXDIS is 0.

• TXDIS: Transmitter Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the transmitter.

• RSTSTA: Reset Status Bits

  Value	Name	Description
  0	-	No effect.
  1	-	Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE, LINSNRE, LINID, LINTC, LINBK, UNRE and RXBRK in US_CSR.

• STTBRK: Start Break

  Value	Name	Description
  0	-	No effect.
  1	-	Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-mitted. No effect if a break is already being transmitted.

• STPBRK: Stop Break

  Value	Name	Description
  0	-	No effect.
  1	-	Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.

• STTTO: Start Time-out

  Value	Name	Description
  0	-	No effect.
  1	-	Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.

• SENDA: Send Address

  Value	Name	Description
  0	-	No effect.
  1	-	In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.

• RSTIT: Reset Iterations

  Value	Name	Description
  0	-	No effect.
  1	-	Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.

• RSTNACK: Reset Non Acknowledge

  Value	Name	Description
  0	-	No effect
  1	-	Resets NACK in US_CSR.

• RETTO: Rearm Time-out

  Value	Name	Description
  0	-	No effect
  1	-	Restart Time-out

• RTSEN: Request to Send Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Drives the pin RTS to 0.

• FCS: Force SPI Chip Select

-

• RTSDIS: Request to Send Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Drives the pin RTS to 1.

• RCS: Release SPI Chip Select

-

• LINABT: Abort LIN Transmission

  Value	Name	Description
  0	-	No effect.
  1	-	Abort the current LIN transmission.

• LINWKUP: Send LIN Wakeup Signal

  Value	Name	Description
  0	-	No effect:
  1	-	Sends a wakeup signal on the LIN bus.

USART2 Mode Register

Name: USART2_MR

Access: read-write

Address: 0x400A0004

31	30	29	28	27	26	25	24
ONEBIT	MODSYNC	MAN	FILTER	-	MAX_ITERATION
23	22	21	20	19	18	17	16
INVDATA	VAR_SYNC	DSNACK	INACK	OVER	CLKO	MODE9	MSBF
15	14	13	12	11	10	9	8
CHMODE		NBSTOP		PAR			SYNC
7	6	5	4	3	2	1	0
CHRL		USCLKS		USART_MODE

• USART_MODE

  Value	Name	Description
  0x0	NORMAL	Normal mode
  0x1	RS485	RS485
  0x2	HW_HANDSHAKING	Hardware Handshaking
  0x4	IS07816_T_0	IS07816 Protocol: T = 0
  0x6	IS07816_T_1	IS07816 Protocol: T = 1
  0x8	IRDA	IrDA
  0xA	LIN_MASTER	LIN Master
  0xB	LIN_SLAVE	LIN Slave
  0xE	SPI_MASTER	SPI Master
  0xF	SPI_SLAVE	SPI Slave

• USCLKS: Clock Selection

  Value	Name	Description
  0x0	MCK	Master Clock MCK is selected
  0x1	DIV	Internal Clock Divided MCK/DIV (DIV=8) is selected
  0x3	SCK	Serial Clock SLK is selected

• CHRL: Character Length.

  Value	Name	Description
  0x0	5_BIT	Character length is 5 bits
  0x1	6_BIT	Character length is 6 bits
  0x2	7_BIT	Character length is 7 bits
  0x3	8_BIT	Character length is 8 bits

• SYNC: Synchronous Mode Select

  Value	Name	Description
  0	-	USART operates in Asynchronous Mode.
  1	-	USART operates in Synchronous Mode.

• CPHA: SPI Clock Phase

-

• PAR: Parity Type

  Value	Name	Description
  0x0	EVEN	Even parity
  0x1	ODD	Odd parity
  0x2	SPACE	Parity forced to 0 (Space)
  0x3	MARK	Parity forced to 1 (Mark)
  0x4	NO	No parity
  0x6	MULTIDROP	Multidrop mode

• NBSTOP: Number of Stop Bits

  Value	Name	Description
  0x0	1_BIT	1 stop bit
  0x1	1_5_BIT	1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
  0x2	2_BIT	2 stop bits

• CHMODE: Channel Mode

  Value	Name	Description
  0x0	NORMAL	Normal Mode
  0x1	AUTOMATIC	Automatic Echo. Receiver input is connected to the TXD pin.
  0x2	LOCAL_LOOPBACK	Local Loopback. Transmitter output is connected to the Receiver Input.
  0x3	REMOTE_LOOPBACK	Remote Loopback. RXD pin is internally connected to the TXD pin.

• MSBF: Bit Order

  Value	Name	Description
  0	-	Least Significant Bit is sent/received first.
  1	-	Most Significant Bit is sent/received first.

• CPOL: SPI Clock Polarity

-

• MODE9: 9-bit Character Length

  Value	Name	Description
  0	-	CHRL defines character length.
  1	-	9-bit character length.

• CLKO: Clock Output Select

  Value	Name	Description
  0	-	The USART does not drive the SCK pin.
  1	-	The USART drives the SCK pin if USCLKS does not select the external clock SCK.

• OVER: Oversampling Mode

  Value	Name	Description
  0	-	16x Oversampling.
  1	-	8x Oversampling.

• INACK: Inhibit Non Acknowledge

  Value	Name	Description
  0	-	The NACK is generated.
  1	-	The NACK is not generated.

• DSNACK: Disable Successive NACK

  Value	Name	Description
  0	-	NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
  1	-	Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.

• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter

  Value	Name	Description
  0	-	User defined configuration of command or data sync field depending on MODSYNC value.
  1	-	The sync field is updated when a character is written into US_THR register.

• INVDATA: INverted Data

  Value	Name	Description
  0	-	The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR is the same as RXD line. Normal mode of operation.
  1	-	The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR regis-ter or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted Mode of operation, useful for contactless card application. To be used with configuration bit MSBF.

• MAX_ITERATION

-

• FILTER: Infrared Receive Line Filter

  Value	Name	Description
  0	-	The USART does not filter the receive line.
  1	-	The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

• MAN: Manchester Encoder/Decoder Enable

  Value	Name	Description
  0	-	Manchester Encoder/Decoder are disabled.
  1	-	Manchester Encoder/Decoder are enabled.

• MODSYNC: Manchester Synchronization Mode

  Value	Name	Description
  0	-	The Manchester Start bit is a 0 to 1 transition
  1	-	The Manchester Start bit is a 1 to 0 transition.

• ONEBIT: Start Frame Delimiter Selector

  Value	Name	Description
  0	-	Start Frame delimiter is COMMAND or DATA SYNC.
  1	-	Start Frame delimiter is One Bit.

USART2 Interrupt Enable Register

Name: USART2_IER

Access: write-only

Address: 0x400A0008

31	30	29	28	27	26	25	24
-	-	LINSNRE	LINCE	LINIPE	LINISFE	LINBE	MANE
23	22	21	20	19	18	17	16
-	-	-	-	CTSIC	-	-	-
15	14	13	12	11	10	9	8
LINTC	LINID	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Enable

-

• TXRDY: TXRDY Interrupt Enable

-

• RXBRK: Receiver Break Interrupt Enable

-

• ENDRX: End of Receive Transfer Interrupt Enable

-

• ENDTX: End of Transmit Interrupt Enable

-

• OVRE: Overrun Error Interrupt Enable

-

• FRAME: Framing Error Interrupt Enable

-

• PARE: Parity Error Interrupt Enable

-

• TIMEOUT: Time-out Interrupt Enable

-

• TXEMPTY: TXEMPTY Interrupt Enable

-

• ITER: Max number of Repetitions Reached

-

• UNRE: SPI Underrun Error

-

• TXBUFE: Buffer Empty Interrupt Enable

-

• RXBUFF: Buffer Full Interrupt Enable

-

• NACK: Non Acknowledge Interrupt Enable

-

• LINBK: LIN Break Sent or LIN Break Received Interrupt Enable

-

• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Enable

-

• LINTC: LIN Transfer Completed Interrupt Enable

-

• CTSIC: Clear to Send Input Change Interrupt Enable

-

• MANE: Manchester Error Interrupt Enable

-

• LINBE: LIN Bus Error Interrupt Enable

-

• LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable

-

• LINIPE: LIN Identifier Parity Interrupt Enable

-

• LINCE: LIN Checksum Error Interrupt Enable

-

• LINSNRE: LIN Slave Not Responding Error Interrupt Enable

-

USART2 Interrupt Disable Register

Name: USART2_IDR

Access: write-only

Address: 0x400A000C

31	30	29	28	27	26	25	24
-	-	LINSNRE	LINCE	LINIPE	LINISFE	LINBE	MANE
23	22	21	20	19	18	17	16
-	-	-	-	CTSIC	-	-	-
15	14	13	12	11	10	9	8
LINTC	LINID	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Disable

-

• TXRDY: TXRDY Interrupt Disable

-

• RXBRK: Receiver Break Interrupt Disable

-

• ENDRX: End of Receive Transfer Interrupt Disable

-

• ENDTX: End of Transmit Interrupt Disable

-

• OVRE: Overrun Error Interrupt Disable

-

• FRAME: Framing Error Interrupt Disable

-

• PARE: Parity Error Interrupt Disable

-

• TIMEOUT: Time-out Interrupt Disable

-

• TXEMPTY: TXEMPTY Interrupt Disable

-

• ITER: Max number of Repetitions Reached Disable

-

• UNRE: SPI Underrun Error Disable

-

• TXBUFE: Buffer Empty Interrupt Disable

-

• RXBUFF: Buffer Full Interrupt Disable

-

• NACK: Non Acknowledge Interrupt Disable

-

• LINBK: LIN Break Sent or LIN Break Received Interrupt Disable

-

• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Disable

-

• LINTC: LIN Transfer Completed Interrupt Disable

-

• CTSIC: Clear to Send Input Change Interrupt Disable

-

• MANE: Manchester Error Interrupt Disable

-

• LINBE: LIN Bus Error Interrupt Disable

-

• LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable

-

• LINIPE: LIN Identifier Parity Interrupt Disable

-

• LINCE: LIN Checksum Error Interrupt Disable

-

• LINSNRE: LIN Slave Not Responding Error Interrupt Disable

-

USART2 Interrupt Mask Register

Name: USART2_IMR

Access: read-only

Address: 0x400A0010

31	30	29	28	27	26	25	24
-	-	LINSNRE	LINCE	LINIPE	LINISFE	LINBE	MANE
23	22	21	20	19	18	17	16
-	-	-	-	CTSIC	-	-	-
15	14	13	12	11	10	9	8
LINTC	LINID	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: RXRDY Interrupt Mask

-

• TXRDY: TXRDY Interrupt Mask

-

• RXBRK: Receiver Break Interrupt Mask

-

• ENDRX: End of Receive Transfer Interrupt Mask

-

• ENDTX: End of Transmit Interrupt Mask

-

• OVRE: Overrun Error Interrupt Mask

-

• FRAME: Framing Error Interrupt Mask

-

• PARE: Parity Error Interrupt Mask

-

• TIMEOUT: Time-out Interrupt Mask

-

• TXEMPTY: TXEMPTY Interrupt Mask

-

• ITER: Max number of Repetitions Reached Mask

-

• UNRE: SPI Underrun Error Mask

-

• TXBUFE: Buffer Empty Interrupt Mask

-

• RXBUFF: Buffer Full Interrupt Mask

-

• NACK: Non Acknowledge Interrupt Mask

-

• LINBK: LIN Break Sent or LIN Break Received Interrupt Mask

-

• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Mask

-

• LINTC: LIN Transfer Completed Interrupt Mask

-

• CTSIC: Clear to Send Input Change Interrupt Mask

-

• MANE: Manchester Error Interrupt Mask

-

• LINBE: LIN Bus Error Interrupt Mask

-

• LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask

-

• LINIPE: LIN Identifier Parity Interrupt Mask

-

• LINCE: LIN Checksum Error Interrupt Mask

-

• LINSNRE: LIN Slave Not Responding Error Interrupt Mask

-

USART2 Channel Status Register

Name: USART2_CSR

Access: read-only

Address: 0x400A0014

31	30	29	28	27	26	25	24
-	-	LINSNRE	LINCE	LINIPE	LINISFE	LINBE	MANERR
23	22	21	20	19	18	17	16
CTS	-	-	-	CTSIC	-	-	-
15	14	13	12	11	10	9	8
LINTC	LINID	NACK	RXBUFF	TXBUFE	ITER	TXEMPTY	TIMEOUT
7	6	5	4	3	2	1	0
PARE	FRAME	OVRE	ENDTX	ENDRX	RXBRK	TXRDY	RXRDY

• RXRDY: Receiver Ready

  Value	Name	Description
  0	-	No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
  1	-	At least one complete character has been received and US_RHR has not yet been read.

• TXRDY: Transmitter Ready

  Value	Name	Description
  0	-	A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
  1	-	There is no character in the US_THR.

• RXBRK: Break Received/End of Break

  Value	Name	Description
  0	-	No Break received or End of Break detected since the last RSTSTA.
  1	-	Break Received or End of Break detected since the last RSTSTA.

• ENDRX: End of Receiver Transfer

  Value	Name	Description
  0	-	The End of Transfer signal from the Receive PDC channel is inactive.
  1	-	The End of Transfer signal from the Receive PDC channel is active.

• ENDTX: End of Transmitter Transfer

  Value	Name	Description
  0	-	The End of Transfer signal from the Transmit PDC channel is inactive.
  1	-	The End of Transfer signal from the Transmit PDC channel is active.

• OVRE: Overrun Error

  Value	Name	Description
  0	-	No overrun error has occurred since the last RSTSTA.
  1	-	At least one overrun error has occurred since the last RSTSTA.

• FRAME: Framing Error

  Value	Name	Description
  0	-	No stop bit has been detected low since the last RSTSTA.
  1	-	At least one stop bit has been detected low since the last RSTSTA.

• PARE: Parity Error

  Value	Name	Description
  0	-	No parity error has been detected since the last RSTSTA.
  1	-	At least one parity error has been detected since the last RSTSTA.

• TIMEOUT: Receiver Time-out

  Value	Name	Description
  0	-	There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
  1	-	There has been a time-out since the last Start Time-out command (STTTO in US_CR).

• TXEMPTY: Transmitter Empty

  Value	Name	Description
  0	-	There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
  1	-	There are no characters in US_THR, nor in the Transmit Shift Register.

• ITER: Max number of Repetitions Reached

  Value	Name	Description
  0	-	Maximum number of repetitions has not been reached since the last RSTSTA.
  1	-	Maximum number of repetitions has been reached since the last RSTSTA.

• UNRE: SPI Underrun Error

-

• TXBUFE: Transmission Buffer Empty

  Value	Name	Description
  0	-	The signal Buffer Empty from the Transmit PDC channel is inactive.
  1	-	The signal Buffer Empty from the Transmit PDC channel is active.

• RXBUFF: Reception Buffer Full

  Value	Name	Description
  0	-	The signal Buffer Full from the Receive PDC channel is inactive.
  1	-	The signal Buffer Full from the Receive PDC channel is active.

• NACK: Non Acknowledge Interrupt

  Value	Name	Description
  0	-	Non Acknowledge has not been detected since the last RSTNACK.
  1	-	At least one Non Acknowledge has been detected since the last RSTNACK.

• LINBK: LIN Break Sent or LIN Break Received

-

• LINID: LIN Identifier Sent or LIN Identifier Received

  Value	Name	Description
  0x0	-	No LIN Identifier has been sent since the last RSTSTA.
  0x1	-	At least one LIN Identifier has been sent since the last RSTSTA.

• LINTC: LIN Transfer Completed

  Value	Name	Description
  0	-	The USART is idle or a LIN transfer is ongoing.
  1	-	A LIN transfer has been completed since the last RSTSTA.

• CTSIC: Clear to Send Input Change Flag

  Value	Name	Description
  0	-	No input change has been detected on the CTS pin since the last read of US_CSR.
  1	-	At least one input change has been detected on the CTS pin since the last read of US_CSR.

• CTS: Image of CTS Input

  Value	Name	Description
  0	-	CTS is set to 0.
  1	-	CTS is set to 1.

• LINBLS: LIN Bus Line Status

  Value	Name	Description
  0	-	LIN Bus Line is set to 0.
  1	-	LIN Bus Line is set to 1.

• MANERR: Manchester Error

  Value	Name	Description
  0	-	No Manchester error has been detected since the last RSTSTA.
  1	-	At least one Manchester error has been detected since the last RSTSTA.

• LINBE: LIN Bit Error

  Value	Name	Description
  0	-	No Bit Error has been detected since the last RSTSTA.
  1	-	A Bit Error has been detected since the last RSTSTA.

• LINISFE: LIN Inconsistent Synch Field Error

  Value	Name	Description
  0	-	No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA
  1	-	The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last RSTSTA.

• LINIPE: LIN Identifier Parity Error

  Value	Name	Description
  0	-	No LIN Identifier Parity Error has been detected since the last RSTSTA.
  1	-	A LIN Identifier Parity Error has been detected since the last RSTSTA.

• LINCE: LIN Checksum Error

  Value	Name	Description
  0	-	No LIN Checksum Error has been detected since the last RSTSTA.
  1	-	A LIN Checksum Error has been detected since the last RSTSTA.

• LINSNRE: LIN Slave Not Responding Error

  Value	Name	Description
  0	-	No LIN Slave Not Responding Error has been detected since the last RSTSTA.
  1	-	A LIN Slave Not Responding Error has been detected since the last RSTSTA.

USART2 Receiver Holding Register

Name: USART2_RHR

Access: read-only

Address: 0x400A0018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXSYNH	-	-	-	-	-	-	RXCHR
7	6	5	4	3	2	1	0
RXCHR

• RXCHR: Received Character

-

• RXSYNH: Received Sync

  Value	Name	Description
  0	-	Last Character received is a Data.
  1	-	Last Character received is a Command.

USART2 Transmitter Holding Register

Name: USART2_THR

Access: write-only

Address: 0x400A001C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXSYNH	-	-	-	-	-	-	TXCHR
7	6	5	4	3	2	1	0
TXCHR

• TXCHR: Character to be Transmitted

-

• TXSYNH: Sync Field to be transmitted

  Value	Name	Description
  0	-	The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
  1	-	The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.

USART2 Baud Rate Generator Register

Name: USART2_BRGR

Access: read-write

Address: 0x400A0020

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	FP
15	14	13	12	11	10	9	8
CD
7	6	5	4	3	2	1	0
CD

• CD: Clock Divider

-

• FP: Fractional Part

-

USART2 Receiver Time-out Register

Name: USART2_RTOR

Access: read-write

Address: 0x400A0024

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	TO
15	14	13	12	11	10	9	8
TO
7	6	5	4	3	2	1	0
TO

• TO: Time-out Value

-

USART2 Transmitter Timeguard Register

Name: USART2_TTGR

Access: read-write

Address: 0x400A0028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
TG

• TG: Timeguard Value

-

USART2 FI DI Ratio Register

Name: USART2_FIDI

Access: read-write

Address: 0x400A0040

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	FI_DI_RATIO
7	6	5	4	3	2	1	0
FI_DI_RATIO

• FI_DI_RATIO: FI Over DI Ratio Value

-

USART2 Number of Errors Register

Name: USART2_NER

Access: read-only

Address: 0x400A0044

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
NB_ERRORS

• NB_ERRORS: Number of Errors

-

USART2 IrDA Filter Register

Name: USART2_IF

Access: read-write

Address: 0x400A004C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
IRDA_FILTER

• IRDA_FILTER: IrDA Filter

-

USART2 Manchester Encoder Decoder Register

Name: USART2_MAN

Access: read-write

Address: 0x400A0050

31	30	29	28	27	26	25	24
-	DRIFT	STUCKTO1	RX_MPOL	-	-	RX_PP
23	22	21	20	19	18	17	16
-	-	-	-	RX_PL
15	14	13	12	11	10	9	8
-	-	-	TX_MPOL	-	-	TX_PP
7	6	5	4	3	2	1	0
-	-	-	-	TX_PL

• TX_PL: Transmitter Preamble Length

-

• TX_PP: Transmitter Preamble Pattern

  Value	Name	Description
  0x0	ALL_ONE	The preamble is composed of '1's
  0x1	ALL_ZERO	The preamble is composed of '0's
  0x2	ZERO_ONE	The preamble is composed of '01's
  0x3	ONE_ZERO	The preamble is composed of '10's

• TX_MPOL: Transmitter Manchester Polarity

  Value	Name	Description
  0	-	Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
  1	-	Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• RX_PL: Receiver Preamble Length

-

• RX_PP: Receiver Preamble Pattern detected

  Value	Name	Description
  0x0	ALL_ONE	The preamble is composed of '1's
  0x1	ALL_ZERO	The preamble is composed of '0's
  0x2	ZERO_ONE	The preamble is composed of '01's
  0x3	ONE_ZERO	The preamble is composed of '10's

• RX_MPOL: Receiver Manchester Polarity

  Value	Name	Description
  0	-	Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
  1	-	Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• STUCKTO1

-

• DRIFT: Drift compensation

  Value	Name	Description
  0	-	The USART can not recover from an important clock drift
  1	-	The USART can recover from clock drift. The 16X clock mode must be enabled.

USART2 LIN Mode Register

Name: USART2_LINMR

Access: read-write

Address: 0x400A0054

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	PDCM
15	14	13	12	11	10	9	8
DLC
7	6	5	4	3	2	1	0
WKUPTYP	FSDIS	DLM	CHKTYP	CHKDIS	PARDIS	NACT

• NACT: LIN Node Action

  Value	Name	Description
  0x0	PUBLISH	The USART transmits the response.
  0x1	SUBSCRIBE	The USART receives the response.
  0x2	IGNORE	The USART does not transmit and does not receive the response.

• PARDIS: Parity Disable

  Value	Name	Description
  0	-	In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configuration, the parity is checked automatically.
  1	-	Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.

• CHKDIS: Checksum Disable

  Value	Name	Description
  0	-	In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the check-sum is checked automatically.
  1	-	Whatever the node configuration is, the checksum is not computed/sent and it is not checked.

• CHKTYP: Checksum Type

  Value	Name	Description
  0	-	LIN 2.0 "Enhanced" Checksum
  1	-	LIN 1.3 "Classic" Checksum

• DLM: Data Length Mode

  Value	Name	Description
  0	-	The response data length is defined by the field DLC of this register.
  1	-	The response data length is defined by the bits 5 and 6 of the Identifier (IDCHR in US_LINIR).

• FSDIS: Frame Slot Mode Disable

  Value	Name	Description
  0	-	The Frame Slot Mode is enabled.
  1	-	The Frame Slot Mode is disabled.

• WKUPTYP: Wakeup Signal Type

  Value	Name	Description
  0	-	setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal.
  1	-	setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal.

• DLC: Data Length Control

-

• PDCM: PDC Mode

  Value	Name	Description
  0	-	The LIN mode register US_LINMR is not written by the PDC.
  1	-	The LIN mode register US_LINMR (excepting that flag) is written by the PDC.

USART2 LIN Identifier Register

Name: USART2_LINIR

Access: read-write

Address: 0x400A0058

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
IDCHR

• IDCHR: Identifier Character

-

USART2 Write Protect Mode Register

Name: USART2_WPMR

Access: read-write

Address: 0x400A00E4

31	30	29	28	27	26	25	24
WPKEY
23	22	21	20	19	18	17	16
WPKEY
15	14	13	12	11	10	9	8
WPKEY
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	WPEN

• WPEN: Write Protect Enable

  Value	Name	Description
  0	-	Disables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).
  1	-	Enables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII).

• WPKEY: Write Protect KEY

-

USART2 Write Protect Status Register

Name: USART2_WPSR

Access: read-only

Address: 0x400A00E8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
WPVSRC
15	14	13	12	11	10	9	8
WPVSRC
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	WPVS

• WPVS: Write Protect Violation Status

  Value	Name	Description
  0	-	No Write Protect Violation has occurred since the last read of the US_WPSR register.
  1	-	A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.

• WPVSRC: Write Protect Violation Source

-

USART2 Receive Pointer Register

Name: USART2_RPR

Access: read-write

Address: 0x400A0100

31	30	29	28	27	26	25	24
RXPTR
23	22	21	20	19	18	17	16
RXPTR
15	14	13	12	11	10	9	8
RXPTR
7	6	5	4	3	2	1	0
RXPTR

• RXPTR: Receive Pointer Register

-

USART2 Receive Counter Register

Name: USART2_RCR

Access: read-write

Address: 0x400A0104

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXCTR
7	6	5	4	3	2	1	0
RXCTR

• RXCTR: Receive Counter Register

-

USART2 Transmit Pointer Register

Name: USART2_TPR

Access: read-write

Address: 0x400A0108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

• TXPTR: Transmit Counter Register

-

USART2 Transmit Counter Register

Name: USART2_TCR

Access: read-write

Address: 0x400A010C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

• TXCTR: Transmit Counter Register

-

USART2 Receive Next Pointer Register

Name: USART2_RNPR

Access: read-write

Address: 0x400A0110

31	30	29	28	27	26	25	24
RXNPTR
23	22	21	20	19	18	17	16
RXNPTR
15	14	13	12	11	10	9	8
RXNPTR
7	6	5	4	3	2	1	0
RXNPTR

• RXNPTR: Receive Next Pointer

-

USART2 Receive Next Counter Register

Name: USART2_RNCR

Access: read-write

Address: 0x400A0114

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
RXNCTR
7	6	5	4	3	2	1	0
RXNCTR

• RXNCTR: Receive Next Counter

-

USART2 Transmit Next Pointer Register

Name: USART2_TNPR

Access: read-write

Address: 0x400A0118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

• TXNPTR: Transmit Next Pointer

-

USART2 Transmit Next Counter Register

Name: USART2_TNCR

Access: read-write

Address: 0x400A011C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCTR
7	6	5	4	3	2	1	0
TXNCTR

• TXNCTR: Transmit Counter Next

-

USART2 Transfer Control Register

Name: USART2_PTCR

Access: write-only

Address: 0x400A0120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables PDC receiver channel requests if RXTDIS is not set.

• RXTDIS: Receiver Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC receiver channel requests.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the PDC transmitter channel requests.

• TXTDIS: Transmitter Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC transmitter channel requests.

USART2 Transfer Status Register

Name: USART2_PTSR

Access: read-only

Address: 0x400A0124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	PDC Receiver channel requests are disabled.
  1	-	PDC Receiver channel requests are enabled.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	PDC Transmitter channel requests are disabled.
  1	-	PDC Transmitter channel requests are enabled.