SAM3XA TC2

Timer Counter (TC2) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x40088000	Channel Control Register (channel = 0)	TC2_CCR0	write-only	-
0x40088004	Channel Mode Register (channel = 0)	TC2_CMR0	read-write	0x00000000
0x40088008	Stepper Motor Mode Register (channel = 0)	TC2_SMMR0	read-write	0x00000000
0x40088010	Counter Value (channel = 0)	TC2_CV0	read-only	0x00000000
0x40088014	Register A (channel = 0)	TC2_RA0	read-write	0x00000000
0x40088018	Register B (channel = 0)	TC2_RB0	read-write	0x00000000
0x4008801C	Register C (channel = 0)	TC2_RC0	read-write	0x00000000
0x40088020	Status Register (channel = 0)	TC2_SR0	read-only	0x00000000
0x40088024	Interrupt Enable Register (channel = 0)	TC2_IER0	write-only	-
0x40088028	Interrupt Disable Register (channel = 0)	TC2_IDR0	write-only	-
0x4008802C	Interrupt Mask Register (channel = 0)	TC2_IMR0	read-only	0x00000000
0x40088040	Channel Control Register (channel = 1)	TC2_CCR1	write-only	-
0x40088044	Channel Mode Register (channel = 1)	TC2_CMR1	read-write	0x00000000
0x40088048	Stepper Motor Mode Register (channel = 1)	TC2_SMMR1	read-write	0x00000000
0x40088050	Counter Value (channel = 1)	TC2_CV1	read-only	0x00000000
0x40088054	Register A (channel = 1)	TC2_RA1	read-write	0x00000000
0x40088058	Register B (channel = 1)	TC2_RB1	read-write	0x00000000
0x4008805C	Register C (channel = 1)	TC2_RC1	read-write	0x00000000
0x40088060	Status Register (channel = 1)	TC2_SR1	read-only	0x00000000
0x40088064	Interrupt Enable Register (channel = 1)	TC2_IER1	write-only	-
0x40088068	Interrupt Disable Register (channel = 1)	TC2_IDR1	write-only	-
0x4008806C	Interrupt Mask Register (channel = 1)	TC2_IMR1	read-only	0x00000000
0x40088080	Channel Control Register (channel = 2)	TC2_CCR2	write-only	-
0x40088084	Channel Mode Register (channel = 2)	TC2_CMR2	read-write	0x00000000
0x40088088	Stepper Motor Mode Register (channel = 2)	TC2_SMMR2	read-write	0x00000000
0x40088090	Counter Value (channel = 2)	TC2_CV2	read-only	0x00000000
0x40088094	Register A (channel = 2)	TC2_RA2	read-write	0x00000000
0x40088098	Register B (channel = 2)	TC2_RB2	read-write	0x00000000
0x4008809C	Register C (channel = 2)	TC2_RC2	read-write	0x00000000
0x400880A0	Status Register (channel = 2)	TC2_SR2	read-only	0x00000000
0x400880A4	Interrupt Enable Register (channel = 2)	TC2_IER2	write-only	-
0x400880A8	Interrupt Disable Register (channel = 2)	TC2_IDR2	write-only	-
0x400880AC	Interrupt Mask Register (channel = 2)	TC2_IMR2	read-only	0x00000000
0x400880C0	Block Control Register	TC2_BCR	write-only	-
0x400880C4	Block Mode Register	TC2_BMR	read-write	0x00000000
0x400880C8	QDEC Interrupt Enable Register	TC2_QIER	write-only	-
0x400880CC	QDEC Interrupt Disable Register	TC2_QIDR	write-only	-
0x400880D0	QDEC Interrupt Mask Register	TC2_QIMR	read-only	0x00000000
0x400880D4	QDEC Interrupt Status Register	TC2_QISR	read-only	0x00000000
0x400880D8	Fault Mode Register	TC2_FMR	read-write	0x00000000
0x400880E4	Write Protect Mode Register	TC2_WPMR	read-write	0x00000000

Register Fields

TC2 Channel Control Register (channel = 0)

Name: TC2_CCR0

Access: write-only

Address: 0x40088000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	SWTRG	CLKDIS	CLKEN

• CLKEN: Counter Clock Enable Command

  Value	Name	Description
  0	-	no effect.
  1	-	enables the clock if CLKDIS is not 1.

• CLKDIS: Counter Clock Disable Command

  Value	Name	Description
  0	-	no effect.
  1	-	disables the clock.

• SWTRG: Software Trigger Command

  Value	Name	Description
  0	-	no effect.
  1	-	a software trigger is performed: the counter is reset and the clock is started.

TC2 Channel Mode Register (channel = 0)

Name: TC2_CMR0

Access: read-write

Address: 0x40088004

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	LDRB		LDRA
15	14	13	12	11	10	9	8
WAVE	CPCTRG	-	-	-	ABETRG	ETRGEDG
7	6	5	4	3	2	1	0
LDBDIS	LDBSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• LDBSTOP: Counter Clock Stopped with RB Loading

  Value	Name	Description
  0	-	counter clock is not stopped when RB loading occurs.
  1	-	counter clock is stopped when RB loading occurs.

• LDBDIS: Counter Clock Disable with RB Loading

  Value	Name	Description
  0	-	counter clock is not disabled when RB loading occurs.
  1	-	counter clock is disabled when RB loading occurs.

• ETRGEDG: External Trigger Edge Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• ABETRG: TIOA or TIOB External Trigger Selection

  Value	Name	Description
  0	-	TIOB is used as an external trigger.
  1	-	TIOA is used as an external trigger.

• CPCTRG: RC Compare Trigger Enable

  Value	Name	Description
  0	-	RC Compare has no effect on the counter and its clock.
  1	-	RC Compare resets the counter and starts the counter clock.

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Capture Mode is enabled.
  1	-	Capture Mode is disabled (Waveform Mode is enabled).

• LDRA: RA Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

• LDRB: RB Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

Alternate: WAVE_EQ_1

31	30	29	28	27	26	25	24
BSWTRG		BEEVT		BCPC		BCPB
23	22	21	20	19	18	17	16
ASWTRG		AEEVT		ACPC		ACPA
15	14	13	12	11	10	9	8
WAVE	WAVSEL		ENETRG	EEVT		EEVTEDG
7	6	5	4	3	2	1	0
CPCDIS	CPCSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• CPCSTOP: Counter Clock Stopped with RC Compare

  Value	Name	Description
  0	-	counter clock is not stopped when counter reaches RC.
  1	-	counter clock is stopped when counter reaches RC.

• CPCDIS: Counter Clock Disable with RC Compare

  Value	Name	Description
  0	-	counter clock is not disabled when counter reaches RC.
  1	-	counter clock is disabled when counter reaches RC.

• EEVTEDG: External Event Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• EEVT: External Event Selection

  Value	Name	Description
  0x0	TIOB	TIOB
  0x1	XC0	XC0
  0x2	XC1	XC1
  0x3	XC2	XC2

• ENETRG: External Event Trigger Enable

  Value	Name	Description
  0	-	the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
  1	-	the external event resets the counter and starts the counter clock.

• WAVSEL: Waveform Selection

  Value	Name	Description
  0x0	UP	UP mode without automatic trigger on RC Compare
  0x1	UPDOWN	UPDOWN mode without automatic trigger on RC Compare
  0x2	UP_RC	UP mode with automatic trigger on RC Compare
  0x3	UPDOWN_RC	UPDOWN mode with automatic trigger on RC Compare

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Waveform Mode is disabled (Capture Mode is enabled).
  1	-	Waveform Mode is enabled.

• ACPA: RA Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ACPC: RC Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• AEEVT: External Event Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ASWTRG: Software Trigger Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPB: RB Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPC: RC Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BEEVT: External Event Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BSWTRG: Software Trigger Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

TC2 Stepper Motor Mode Register (channel = 0)

Name: TC2_SMMR0

Access: read-write

Address: 0x40088008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	DOWN	GCEN

• GCEN: Gray Count Enable

  Value	Name	Description
  0	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
  1	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.

• DOWN: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

TC2 Counter Value (channel = 0)

Name: TC2_CV0

Access: read-only

Address: 0x40088010

31	30	29	28	27	26	25	24
CV
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Counter Value

-

TC2 Register A (channel = 0)

Name: TC2_RA0

Access: read-write

Address: 0x40088014

31	30	29	28	27	26	25	24
RA
23	22	21	20	19	18	17	16
RA
15	14	13	12	11	10	9	8
RA
7	6	5	4	3	2	1	0
RA

• RA: Register A

-

TC2 Register B (channel = 0)

Name: TC2_RB0

Access: read-write

Address: 0x40088018

31	30	29	28	27	26	25	24
RB
23	22	21	20	19	18	17	16
RB
15	14	13	12	11	10	9	8
RB
7	6	5	4	3	2	1	0
RB

• RB: Register B

-

TC2 Register C (channel = 0)

Name: TC2_RC0

Access: read-write

Address: 0x4008801C

31	30	29	28	27	26	25	24
RC
23	22	21	20	19	18	17	16
RC
15	14	13	12	11	10	9	8
RC
7	6	5	4	3	2	1	0
RC

• RC: Register C

-

TC2 Status Register (channel = 0)

Name: TC2_SR0

Access: read-only

Address: 0x40088020

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	MTIOB	MTIOA	CLKSTA
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow Status

  Value	Name	Description
  0	-	no counter overflow has occurred since the last read of the Status Register.
  1	-	a counter overflow has occurred since the last read of the Status Register.

• LOVRS: Load Overrun Status

  Value	Name	Description
  0	-	Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.

• CPAS: RA Compare Status

  Value	Name	Description
  0	-	RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPBS: RB Compare Status

  Value	Name	Description
  0	-	RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPCS: RC Compare Status

  Value	Name	Description
  0	-	RC Compare has not occurred since the last read of the Status Register.
  1	-	RC Compare has occurred since the last read of the Status Register.

• LDRAS: RA Loading Status

  Value	Name	Description
  0	-	RA Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA Load has occurred since the last read of the Status Register, if WAVE = 0.

• LDRBS: RB Loading Status

  Value	Name	Description
  0	-	RB Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RB Load has occurred since the last read of the Status Register, if WAVE = 0.

• ETRGS: External Trigger Status

  Value	Name	Description
  0	-	external trigger has not occurred since the last read of the Status Register.
  1	-	external trigger has occurred since the last read of the Status Register.

• CLKSTA: Clock Enabling Status

  Value	Name	Description
  0	-	clock is disabled.
  1	-	clock is enabled.

• MTIOA: TIOA Mirror

  Value	Name	Description
  0	-	TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
  1	-	TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

• MTIOB: TIOB Mirror

  Value	Name	Description
  0	-	TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
  1	-	TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

TC2 Interrupt Enable Register (channel = 0)

Name: TC2_IER0

Access: write-only

Address: 0x40088024

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Load Overrun Interrupt.

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Compare Interrupt.

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Compare Interrupt.

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Load Interrupt.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Load Interrupt.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	enables the External Trigger Interrupt.

TC2 Interrupt Disable Register (channel = 0)

Name: TC2_IDR0

Access: write-only

Address: 0x40088028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Load Overrun Interrupt (if WAVE = 0).

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Compare Interrupt (if WAVE = 1).

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Compare Interrupt (if WAVE = 1).

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Load Interrupt (if WAVE = 0).

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Load Interrupt (if WAVE = 0).

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	disables the External Trigger Interrupt.

TC2 Interrupt Mask Register (channel = 0)

Name: TC2_IMR0

Access: read-only

Address: 0x4008802C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	the Counter Overflow Interrupt is disabled.
  1	-	the Counter Overflow Interrupt is enabled.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	the Load Overrun Interrupt is disabled.
  1	-	the Load Overrun Interrupt is enabled.

• CPAS: RA Compare

  Value	Name	Description
  0	-	the RA Compare Interrupt is disabled.
  1	-	the RA Compare Interrupt is enabled.

• CPBS: RB Compare

  Value	Name	Description
  0	-	the RB Compare Interrupt is disabled.
  1	-	the RB Compare Interrupt is enabled.

• CPCS: RC Compare

  Value	Name	Description
  0	-	the RC Compare Interrupt is disabled.
  1	-	the RC Compare Interrupt is enabled.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	the Load RA Interrupt is disabled.
  1	-	the Load RA Interrupt is enabled.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	the Load RB Interrupt is disabled.
  1	-	the Load RB Interrupt is enabled.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	the External Trigger Interrupt is disabled.
  1	-	the External Trigger Interrupt is enabled.

TC2 Channel Control Register (channel = 1)

Name: TC2_CCR1

Access: write-only

Address: 0x40088040

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	SWTRG	CLKDIS	CLKEN

• CLKEN: Counter Clock Enable Command

  Value	Name	Description
  0	-	no effect.
  1	-	enables the clock if CLKDIS is not 1.

• CLKDIS: Counter Clock Disable Command

  Value	Name	Description
  0	-	no effect.
  1	-	disables the clock.

• SWTRG: Software Trigger Command

  Value	Name	Description
  0	-	no effect.
  1	-	a software trigger is performed: the counter is reset and the clock is started.

TC2 Channel Mode Register (channel = 1)

Name: TC2_CMR1

Access: read-write

Address: 0x40088044

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	LDRB		LDRA
15	14	13	12	11	10	9	8
WAVE	CPCTRG	-	-	-	ABETRG	ETRGEDG
7	6	5	4	3	2	1	0
LDBDIS	LDBSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• LDBSTOP: Counter Clock Stopped with RB Loading

  Value	Name	Description
  0	-	counter clock is not stopped when RB loading occurs.
  1	-	counter clock is stopped when RB loading occurs.

• LDBDIS: Counter Clock Disable with RB Loading

  Value	Name	Description
  0	-	counter clock is not disabled when RB loading occurs.
  1	-	counter clock is disabled when RB loading occurs.

• ETRGEDG: External Trigger Edge Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• ABETRG: TIOA or TIOB External Trigger Selection

  Value	Name	Description
  0	-	TIOB is used as an external trigger.
  1	-	TIOA is used as an external trigger.

• CPCTRG: RC Compare Trigger Enable

  Value	Name	Description
  0	-	RC Compare has no effect on the counter and its clock.
  1	-	RC Compare resets the counter and starts the counter clock.

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Capture Mode is enabled.
  1	-	Capture Mode is disabled (Waveform Mode is enabled).

• LDRA: RA Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

• LDRB: RB Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

Alternate: WAVE_EQ_1

31	30	29	28	27	26	25	24
BSWTRG		BEEVT		BCPC		BCPB
23	22	21	20	19	18	17	16
ASWTRG		AEEVT		ACPC		ACPA
15	14	13	12	11	10	9	8
WAVE	WAVSEL		ENETRG	EEVT		EEVTEDG
7	6	5	4	3	2	1	0
CPCDIS	CPCSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• CPCSTOP: Counter Clock Stopped with RC Compare

  Value	Name	Description
  0	-	counter clock is not stopped when counter reaches RC.
  1	-	counter clock is stopped when counter reaches RC.

• CPCDIS: Counter Clock Disable with RC Compare

  Value	Name	Description
  0	-	counter clock is not disabled when counter reaches RC.
  1	-	counter clock is disabled when counter reaches RC.

• EEVTEDG: External Event Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• EEVT: External Event Selection

  Value	Name	Description
  0x0	TIOB	TIOB
  0x1	XC0	XC0
  0x2	XC1	XC1
  0x3	XC2	XC2

• ENETRG: External Event Trigger Enable

  Value	Name	Description
  0	-	the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
  1	-	the external event resets the counter and starts the counter clock.

• WAVSEL: Waveform Selection

  Value	Name	Description
  0x0	UP	UP mode without automatic trigger on RC Compare
  0x1	UPDOWN	UPDOWN mode without automatic trigger on RC Compare
  0x2	UP_RC	UP mode with automatic trigger on RC Compare
  0x3	UPDOWN_RC	UPDOWN mode with automatic trigger on RC Compare

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Waveform Mode is disabled (Capture Mode is enabled).
  1	-	Waveform Mode is enabled.

• ACPA: RA Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ACPC: RC Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• AEEVT: External Event Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ASWTRG: Software Trigger Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPB: RB Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPC: RC Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BEEVT: External Event Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BSWTRG: Software Trigger Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

TC2 Stepper Motor Mode Register (channel = 1)

Name: TC2_SMMR1

Access: read-write

Address: 0x40088048

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	DOWN	GCEN

• GCEN: Gray Count Enable

  Value	Name	Description
  0	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
  1	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.

• DOWN: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

TC2 Counter Value (channel = 1)

Name: TC2_CV1

Access: read-only

Address: 0x40088050

31	30	29	28	27	26	25	24
CV
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Counter Value

-

TC2 Register A (channel = 1)

Name: TC2_RA1

Access: read-write

Address: 0x40088054

31	30	29	28	27	26	25	24
RA
23	22	21	20	19	18	17	16
RA
15	14	13	12	11	10	9	8
RA
7	6	5	4	3	2	1	0
RA

• RA: Register A

-

TC2 Register B (channel = 1)

Name: TC2_RB1

Access: read-write

Address: 0x40088058

31	30	29	28	27	26	25	24
RB
23	22	21	20	19	18	17	16
RB
15	14	13	12	11	10	9	8
RB
7	6	5	4	3	2	1	0
RB

• RB: Register B

-

TC2 Register C (channel = 1)

Name: TC2_RC1

Access: read-write

Address: 0x4008805C

31	30	29	28	27	26	25	24
RC
23	22	21	20	19	18	17	16
RC
15	14	13	12	11	10	9	8
RC
7	6	5	4	3	2	1	0
RC

• RC: Register C

-

TC2 Status Register (channel = 1)

Name: TC2_SR1

Access: read-only

Address: 0x40088060

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	MTIOB	MTIOA	CLKSTA
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow Status

  Value	Name	Description
  0	-	no counter overflow has occurred since the last read of the Status Register.
  1	-	a counter overflow has occurred since the last read of the Status Register.

• LOVRS: Load Overrun Status

  Value	Name	Description
  0	-	Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.

• CPAS: RA Compare Status

  Value	Name	Description
  0	-	RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPBS: RB Compare Status

  Value	Name	Description
  0	-	RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPCS: RC Compare Status

  Value	Name	Description
  0	-	RC Compare has not occurred since the last read of the Status Register.
  1	-	RC Compare has occurred since the last read of the Status Register.

• LDRAS: RA Loading Status

  Value	Name	Description
  0	-	RA Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA Load has occurred since the last read of the Status Register, if WAVE = 0.

• LDRBS: RB Loading Status

  Value	Name	Description
  0	-	RB Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RB Load has occurred since the last read of the Status Register, if WAVE = 0.

• ETRGS: External Trigger Status

  Value	Name	Description
  0	-	external trigger has not occurred since the last read of the Status Register.
  1	-	external trigger has occurred since the last read of the Status Register.

• CLKSTA: Clock Enabling Status

  Value	Name	Description
  0	-	clock is disabled.
  1	-	clock is enabled.

• MTIOA: TIOA Mirror

  Value	Name	Description
  0	-	TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
  1	-	TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

• MTIOB: TIOB Mirror

  Value	Name	Description
  0	-	TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
  1	-	TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

TC2 Interrupt Enable Register (channel = 1)

Name: TC2_IER1

Access: write-only

Address: 0x40088064

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Load Overrun Interrupt.

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Compare Interrupt.

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Compare Interrupt.

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Load Interrupt.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Load Interrupt.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	enables the External Trigger Interrupt.

TC2 Interrupt Disable Register (channel = 1)

Name: TC2_IDR1

Access: write-only

Address: 0x40088068

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Load Overrun Interrupt (if WAVE = 0).

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Compare Interrupt (if WAVE = 1).

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Compare Interrupt (if WAVE = 1).

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Load Interrupt (if WAVE = 0).

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Load Interrupt (if WAVE = 0).

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	disables the External Trigger Interrupt.

TC2 Interrupt Mask Register (channel = 1)

Name: TC2_IMR1

Access: read-only

Address: 0x4008806C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	the Counter Overflow Interrupt is disabled.
  1	-	the Counter Overflow Interrupt is enabled.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	the Load Overrun Interrupt is disabled.
  1	-	the Load Overrun Interrupt is enabled.

• CPAS: RA Compare

  Value	Name	Description
  0	-	the RA Compare Interrupt is disabled.
  1	-	the RA Compare Interrupt is enabled.

• CPBS: RB Compare

  Value	Name	Description
  0	-	the RB Compare Interrupt is disabled.
  1	-	the RB Compare Interrupt is enabled.

• CPCS: RC Compare

  Value	Name	Description
  0	-	the RC Compare Interrupt is disabled.
  1	-	the RC Compare Interrupt is enabled.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	the Load RA Interrupt is disabled.
  1	-	the Load RA Interrupt is enabled.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	the Load RB Interrupt is disabled.
  1	-	the Load RB Interrupt is enabled.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	the External Trigger Interrupt is disabled.
  1	-	the External Trigger Interrupt is enabled.

TC2 Channel Control Register (channel = 2)

Name: TC2_CCR2

Access: write-only

Address: 0x40088080

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	SWTRG	CLKDIS	CLKEN

• CLKEN: Counter Clock Enable Command

  Value	Name	Description
  0	-	no effect.
  1	-	enables the clock if CLKDIS is not 1.

• CLKDIS: Counter Clock Disable Command

  Value	Name	Description
  0	-	no effect.
  1	-	disables the clock.

• SWTRG: Software Trigger Command

  Value	Name	Description
  0	-	no effect.
  1	-	a software trigger is performed: the counter is reset and the clock is started.

TC2 Channel Mode Register (channel = 2)

Name: TC2_CMR2

Access: read-write

Address: 0x40088084

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	LDRB		LDRA
15	14	13	12	11	10	9	8
WAVE	CPCTRG	-	-	-	ABETRG	ETRGEDG
7	6	5	4	3	2	1	0
LDBDIS	LDBSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• LDBSTOP: Counter Clock Stopped with RB Loading

  Value	Name	Description
  0	-	counter clock is not stopped when RB loading occurs.
  1	-	counter clock is stopped when RB loading occurs.

• LDBDIS: Counter Clock Disable with RB Loading

  Value	Name	Description
  0	-	counter clock is not disabled when RB loading occurs.
  1	-	counter clock is disabled when RB loading occurs.

• ETRGEDG: External Trigger Edge Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• ABETRG: TIOA or TIOB External Trigger Selection

  Value	Name	Description
  0	-	TIOB is used as an external trigger.
  1	-	TIOA is used as an external trigger.

• CPCTRG: RC Compare Trigger Enable

  Value	Name	Description
  0	-	RC Compare has no effect on the counter and its clock.
  1	-	RC Compare resets the counter and starts the counter clock.

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Capture Mode is enabled.
  1	-	Capture Mode is disabled (Waveform Mode is enabled).

• LDRA: RA Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

• LDRB: RB Loading Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge of TIOA
  0x2	FALLING	Falling edge of TIOA
  0x3	EDGE	Each edge of TIOA

Alternate: WAVE_EQ_1

31	30	29	28	27	26	25	24
BSWTRG		BEEVT		BCPC		BCPB
23	22	21	20	19	18	17	16
ASWTRG		AEEVT		ACPC		ACPA
15	14	13	12	11	10	9	8
WAVE	WAVSEL		ENETRG	EEVT		EEVTEDG
7	6	5	4	3	2	1	0
CPCDIS	CPCSTOP	BURST		CLKI	TCCLKS

• TCCLKS: Clock Selection

  Value	Name	Description
  0x0	TIMER_CLOCK1	Clock selected: TCLK1
  0x1	TIMER_CLOCK2	Clock selected: TCLK2
  0x2	TIMER_CLOCK3	Clock selected: TCLK3
  0x3	TIMER_CLOCK4	Clock selected: TCLK4
  0x4	TIMER_CLOCK5	Clock selected: TCLK5
  0x5	XC0	Clock selected: XC0
  0x6	XC1	Clock selected: XC1
  0x7	XC2	Clock selected: XC2

• CLKI: Clock Invert

  Value	Name	Description
  0	-	counter is incremented on rising edge of the clock.
  1	-	counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

  Value	Name	Description
  0x0	NONE	The clock is not gated by an external signal.
  0x1	XC0	XC0 is ANDed with the selected clock.
  0x2	XC1	XC1 is ANDed with the selected clock.
  0x3	XC2	XC2 is ANDed with the selected clock.

• CPCSTOP: Counter Clock Stopped with RC Compare

  Value	Name	Description
  0	-	counter clock is not stopped when counter reaches RC.
  1	-	counter clock is stopped when counter reaches RC.

• CPCDIS: Counter Clock Disable with RC Compare

  Value	Name	Description
  0	-	counter clock is not disabled when counter reaches RC.
  1	-	counter clock is disabled when counter reaches RC.

• EEVTEDG: External Event Edge Selection

  Value	Name	Description
  0x0	NONE	None
  0x1	RISING	Rising edge
  0x2	FALLING	Falling edge
  0x3	EDGE	Each edge

• EEVT: External Event Selection

  Value	Name	Description
  0x0	TIOB	TIOB
  0x1	XC0	XC0
  0x2	XC1	XC1
  0x3	XC2	XC2

• ENETRG: External Event Trigger Enable

  Value	Name	Description
  0	-	the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
  1	-	the external event resets the counter and starts the counter clock.

• WAVSEL: Waveform Selection

  Value	Name	Description
  0x0	UP	UP mode without automatic trigger on RC Compare
  0x1	UPDOWN	UPDOWN mode without automatic trigger on RC Compare
  0x2	UP_RC	UP mode with automatic trigger on RC Compare
  0x3	UPDOWN_RC	UPDOWN mode with automatic trigger on RC Compare

• WAVE: Waveform Mode

  Value	Name	Description
  0	-	Waveform Mode is disabled (Capture Mode is enabled).
  1	-	Waveform Mode is enabled.

• ACPA: RA Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ACPC: RC Compare Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• AEEVT: External Event Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• ASWTRG: Software Trigger Effect on TIOA

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPB: RB Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BCPC: RC Compare Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BEEVT: External Event Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

• BSWTRG: Software Trigger Effect on TIOB

  Value	Name	Description
  0x0	NONE	None
  0x1	SET	Set
  0x2	CLEAR	Clear
  0x3	TOGGLE	Toggle

TC2 Stepper Motor Mode Register (channel = 2)

Name: TC2_SMMR2

Access: read-write

Address: 0x40088088

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	DOWN	GCEN

• GCEN: Gray Count Enable

  Value	Name	Description
  0	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
  1	-	TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.

• DOWN: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

TC2 Counter Value (channel = 2)

Name: TC2_CV2

Access: read-only

Address: 0x40088090

31	30	29	28	27	26	25	24
CV
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Counter Value

-

TC2 Register A (channel = 2)

Name: TC2_RA2

Access: read-write

Address: 0x40088094

31	30	29	28	27	26	25	24
RA
23	22	21	20	19	18	17	16
RA
15	14	13	12	11	10	9	8
RA
7	6	5	4	3	2	1	0
RA

• RA: Register A

-

TC2 Register B (channel = 2)

Name: TC2_RB2

Access: read-write

Address: 0x40088098

31	30	29	28	27	26	25	24
RB
23	22	21	20	19	18	17	16
RB
15	14	13	12	11	10	9	8
RB
7	6	5	4	3	2	1	0
RB

• RB: Register B

-

TC2 Register C (channel = 2)

Name: TC2_RC2

Access: read-write

Address: 0x4008809C

31	30	29	28	27	26	25	24
RC
23	22	21	20	19	18	17	16
RC
15	14	13	12	11	10	9	8
RC
7	6	5	4	3	2	1	0
RC

• RC: Register C

-

TC2 Status Register (channel = 2)

Name: TC2_SR2

Access: read-only

Address: 0x400880A0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	MTIOB	MTIOA	CLKSTA
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow Status

  Value	Name	Description
  0	-	no counter overflow has occurred since the last read of the Status Register.
  1	-	a counter overflow has occurred since the last read of the Status Register.

• LOVRS: Load Overrun Status

  Value	Name	Description
  0	-	Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.

• CPAS: RA Compare Status

  Value	Name	Description
  0	-	RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPBS: RB Compare Status

  Value	Name	Description
  0	-	RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
  1	-	RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPCS: RC Compare Status

  Value	Name	Description
  0	-	RC Compare has not occurred since the last read of the Status Register.
  1	-	RC Compare has occurred since the last read of the Status Register.

• LDRAS: RA Loading Status

  Value	Name	Description
  0	-	RA Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RA Load has occurred since the last read of the Status Register, if WAVE = 0.

• LDRBS: RB Loading Status

  Value	Name	Description
  0	-	RB Load has not occurred since the last read of the Status Register or WAVE = 1.
  1	-	RB Load has occurred since the last read of the Status Register, if WAVE = 0.

• ETRGS: External Trigger Status

  Value	Name	Description
  0	-	external trigger has not occurred since the last read of the Status Register.
  1	-	external trigger has occurred since the last read of the Status Register.

• CLKSTA: Clock Enabling Status

  Value	Name	Description
  0	-	clock is disabled.
  1	-	clock is enabled.

• MTIOA: TIOA Mirror

  Value	Name	Description
  0	-	TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
  1	-	TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

• MTIOB: TIOB Mirror

  Value	Name	Description
  0	-	TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
  1	-	TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

TC2 Interrupt Enable Register (channel = 2)

Name: TC2_IER2

Access: write-only

Address: 0x400880A4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	enables the Load Overrun Interrupt.

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Compare Interrupt.

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Compare Interrupt.

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RA Load Interrupt.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	enables the RB Load Interrupt.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	enables the External Trigger Interrupt.

TC2 Interrupt Disable Register (channel = 2)

Name: TC2_IDR2

Access: write-only

Address: 0x400880A8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	no effect.
  1	-	disables the Load Overrun Interrupt (if WAVE = 0).

• CPAS: RA Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Compare Interrupt (if WAVE = 1).

• CPBS: RB Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Compare Interrupt (if WAVE = 1).

• CPCS: RC Compare

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RC Compare Interrupt.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RA Load Interrupt (if WAVE = 0).

• LDRBS: RB Loading

  Value	Name	Description
  0	-	no effect.
  1	-	disables the RB Load Interrupt (if WAVE = 0).

• ETRGS: External Trigger

  Value	Name	Description
  0	-	no effect.
  1	-	disables the External Trigger Interrupt.

TC2 Interrupt Mask Register (channel = 2)

Name: TC2_IMR2

Access: read-only

Address: 0x400880AC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
ETRGS	LDRBS	LDRAS	CPCS	CPBS	CPAS	LOVRS	COVFS

• COVFS: Counter Overflow

  Value	Name	Description
  0	-	the Counter Overflow Interrupt is disabled.
  1	-	the Counter Overflow Interrupt is enabled.

• LOVRS: Load Overrun

  Value	Name	Description
  0	-	the Load Overrun Interrupt is disabled.
  1	-	the Load Overrun Interrupt is enabled.

• CPAS: RA Compare

  Value	Name	Description
  0	-	the RA Compare Interrupt is disabled.
  1	-	the RA Compare Interrupt is enabled.

• CPBS: RB Compare

  Value	Name	Description
  0	-	the RB Compare Interrupt is disabled.
  1	-	the RB Compare Interrupt is enabled.

• CPCS: RC Compare

  Value	Name	Description
  0	-	the RC Compare Interrupt is disabled.
  1	-	the RC Compare Interrupt is enabled.

• LDRAS: RA Loading

  Value	Name	Description
  0	-	the Load RA Interrupt is disabled.
  1	-	the Load RA Interrupt is enabled.

• LDRBS: RB Loading

  Value	Name	Description
  0	-	the Load RB Interrupt is disabled.
  1	-	the Load RB Interrupt is enabled.

• ETRGS: External Trigger

  Value	Name	Description
  0	-	the External Trigger Interrupt is disabled.
  1	-	the External Trigger Interrupt is enabled.

TC2 Block Control Register

Name: TC2_BCR

Access: write-only

Address: 0x400880C0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	SYNC

• SYNC: Synchro Command

  Value	Name	Description
  0	-	no effect.
  1	-	asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.

TC2 Block Mode Register

Name: TC2_BMR

Access: read-write

Address: 0x400880C4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	MAXFILT
23	22	21	20	19	18	17	16
MAXFILT				FILTER	-	IDXPHB	SWAP
15	14	13	12	11	10	9	8
INVIDX	INVB	INVA	EDGPHA	QDTRANS	SPEEDEN	POSEN	QDEN
7	6	5	4	3	2	1	0
-	-	TC2XC2S		TC1XC1S		TC0XC0S

• TC0XC0S: External Clock Signal 0 Selection

  Value	Name	Description
  0x0	TCLK0	Signal connected to XC0: TCLK0
  0x2	TIOA1	Signal connected to XC0: TIOA1
  0x3	TIOA2	Signal connected to XC0: TIOA2

• TC1XC1S: External Clock Signal 1 Selection

  Value	Name	Description
  0x0	TCLK1	Signal connected to XC1: TCLK1
  0x2	TIOA0	Signal connected to XC1: TIOA0
  0x3	TIOA2	Signal connected to XC1: TIOA2

• TC2XC2S: External Clock Signal 2 Selection

  Value	Name	Description
  0x0	TCLK2	Signal connected to XC2: TCLK2
  0x2	TIOA1	Signal connected to XC2: TIOA1
  0x3	TIOA2	Signal connected to XC2: TIOA2

• QDEN: Quadrature Decoder ENabled

  Value	Name	Description
  0	-	disabled.
  1	-	enables the quadrature decoder logic (filter, edge detection and quadrature decoding).

• POSEN: POSition ENabled

  Value	Name	Description
  0	-	disable position.
  1	-	enables the position measure on channel 0 and 1

• SPEEDEN: SPEED ENabled

  Value	Name	Description
  0	-	disabled.
  1	-	enables the speed measure on channel 0, the time base being provided by channel 2.

• QDTRANS: Quadrature Decoding TRANSparent

  Value	Name	Description
  0	-	full quadrature decoding logic is active (direction change detected).
  1	-	quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.

• EDGPHA: EDGe on PHA count mode

  Value	Name	Description
  0	-	edges are detected on both PHA and PHB.
  1	-	edges are detected on PHA only.

• INVA: INVerted phA

  Value	Name	Description
  0	-	PHA (TIOA0) is directly driving quadrature decoder logic.
  1	-	PHA is inverted before driving quadrature decoder logic.

• INVB: INVerted phB

  Value	Name	Description
  0	-	PHB (TIOB0) is directly driving quadrature decoder logic.
  1	-	PHB is inverted before driving quadrature decoder logic.

• INVIDX: INVerted InDeX

  Value	Name	Description
  0	-	IDX (TIOA1) is directly driving quadrature logic.
  1	-	IDX is inverted before driving quadrature logic.

• SWAP: SWAP PHA and PHB

  Value	Name	Description
  0	-	no swap between PHA and PHB.
  1	-	swap PHA and PHB internally, prior to driving quadrature decoder logic.

• IDXPHB: InDeX pin is PHB pin

  Value	Name	Description
  0	-	IDX pin of the rotary sensor must drive TIOA1.
  1	-	IDX pin of the rotary sensor must drive TIOB0.

• FILTER

  Value	Name	Description
  0	-	IDX,PHA, PHB input pins are not filtered.
  1	-	IDX,PHA, PHB input pins are filtered using MAXFILT value.

• MAXFILT: MAXimum FILTer

-

TC2 QDEC Interrupt Enable Register

Name: TC2_QIER

Access: write-only

Address: 0x400880C8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	QERR	DIRCHG	IDX

• IDX: InDeX

  Value	Name	Description
  0	-	no effect.
  1	-	enables the interrupt when a rising edge occurs on IDX input.

• DIRCHG: DIRection CHanGe

  Value	Name	Description
  0	-	no effect.
  1	-	enables the interrupt when a change on rotation direction is detected.

• QERR: Quadrature ERRor

  Value	Name	Description
  0	-	no effect.
  1	-	enables the interrupt when a quadrature error occurs on PHA,PHB.

TC2 QDEC Interrupt Disable Register

Name: TC2_QIDR

Access: write-only

Address: 0x400880CC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	QERR	DIRCHG	IDX

• IDX: InDeX

  Value	Name	Description
  0	-	no effect.
  1	-	disables the interrupt when a rising edge occurs on IDX input.

• DIRCHG: DIRection CHanGe

  Value	Name	Description
  0	-	no effect.
  1	-	disables the interrupt when a change on rotation direction is detected.

• QERR: Quadrature ERRor

  Value	Name	Description
  0	-	no effect.
  1	-	disables the interrupt when a quadrature error occurs on PHA, PHB.

TC2 QDEC Interrupt Mask Register

Name: TC2_QIMR

Access: read-only

Address: 0x400880D0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	QERR	DIRCHG	IDX

• IDX: InDeX

  Value	Name	Description
  0	-	the interrupt on IDX input is disabled.
  1	-	the interrupt on IDX input is enabled.

• DIRCHG: DIRection CHanGe

  Value	Name	Description
  0	-	the interrupt on rotation direction change is disabled.
  1	-	the interrupt on rotation direction change is enabled.

• QERR: Quadrature ERRor

  Value	Name	Description
  0	-	the interrupt on quadrature error is disabled.
  1	-	the interrupt on quadrature error is enabled.

TC2 QDEC Interrupt Status Register

Name: TC2_QISR

Access: read-only

Address: 0x400880D4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	DIR
7	6	5	4	3	2	1	0
-	-	-	-	-	QERR	DIRCHG	IDX

• IDX: InDeX

  Value	Name	Description
  0	-	no Index input change since the last read of TC_QISR.
  1	-	the IDX input has change since the last read of TC_QISR.

• DIRCHG: DIRection CHanGe

  Value	Name	Description
  0	-	no change on rotation direction since the last read of TC_QISR.
  1	-	the rotation direction changed since the last read of TC_QISR.

• QERR: Quadrature ERRor

  Value	Name	Description
  0	-	no quadrature error since the last read of TC_QISR.
  1	-	A quadrature error occurred since the last read of TC_QISR.

• DIR: Direction

-

TC2 Fault Mode Register

Name: TC2_FMR

Access: read-write

Address: 0x400880D8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	ENCF1	ENCF0

• ENCF0: ENable Compare Fault Channel 0

  Value	Name	Description
  0	-	disables the FAULT output source (CPCS flag) from channel 0.
  1	-	enables the FAULT output source (CPCS flag) from channel 0.

• ENCF1: ENable Compare Fault Channel 1

  Value	Name	Description
  0	-	disables the FAULT output source (CPCS flag) from channel 1.
  1	-	enables the FAULT output source (CPCS flag) from channel 1.

TC2 Write Protect Mode Register

Name: TC2_WPMR

Access: read-write

Address: 0x400880E4

31	30	29	28	27	26	25	24
WPKEY
23	22	21	20	19	18	17	16
WPKEY
15	14	13	12	11	10	9	8
WPKEY
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	WPEN

• WPEN: Write Protect Enable

  Value	Name	Description
  0	-	disables the Write Protect if WPKEY corresponds to 0x54494D ("TIM" in ASCII).
  1	-	enables the Write Protect if WPKEY corresponds to 0x54494D ("TIM" in ASCII).

• WPKEY: Write Protect KEY

-