SAM3XA SDRAMC

SDRAM Controller (SDRAMC) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x400E0200	SDRAMC Mode Register	SDRAMC_MR	read-write	0x00000000
0x400E0204	SDRAMC Refresh Timer Register	SDRAMC_TR	read-write	0x00000000
0x400E0208	SDRAMC Configuration Register	SDRAMC_CR	read-write	0x852372C0
0x400E0210	SDRAMC Low Power Register	SDRAMC_LPR	read-write	0x00000000
0x400E0214	SDRAMC Interrupt Enable Register	SDRAMC_IER	write-only	-
0x400E0218	SDRAMC Interrupt Disable Register	SDRAMC_IDR	write-only	-
0x400E021C	SDRAMC Interrupt Mask Register	SDRAMC_IMR	read-only	0x00000000
0x400E0220	SDRAMC Interrupt Status Register	SDRAMC_ISR	read-only	0x00000000
0x400E0224	SDRAMC Memory Device Register	SDRAMC_MDR	read-write	0x00000000
0x400E0228	SDRAMC Configuration Register 1	SDRAMC_CR1	read-write	0x00000002
0x400E022C	SDRAMC OCMS Register 1	SDRAMC_OCMS	read-write	0x00000000

Register Fields

SDRAMC SDRAMC Mode Register

Name: SDRAMC_MR

Access: read-write

Address: 0x400E0200

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	MODE

• MODE: SDRAMC Command Mode

  Value	Name	Description
  0x0	NORMAL	Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM.
  0x1	NOP	The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
  0x2	ALLBANKS_PRECHARGE	The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
  0x3	LOAD_MODEREG	The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
  0x4	AUTO_REFRESH	The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM.
  0x5	EXT_LOAD_MODEREG	The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1.
  0x6	DEEP_POWERDOWN	Deep power-down mode. Enters deep power-down mode.

SDRAMC SDRAMC Refresh Timer Register

Name: SDRAMC_TR

Access: read-write

Address: 0x400E0204

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	COUNT
7	6	5	4	3	2	1	0
COUNT

• COUNT: SDRAMC Refresh Timer Count

-

SDRAMC SDRAMC Configuration Register

Name: SDRAMC_CR

Access: read-write

Address: 0x400E0208

31	30	29	28	27	26	25	24
TXSR				TRAS
23	22	21	20	19	18	17	16
TRCD				TRP
15	14	13	12	11	10	9	8
TRC_TRFC				TWR
7	6	5	4	3	2	1	0
DBW	CAS		NB	NR		NC

• NC: Number of Column Bits

  Value	Name	Description
  0x0	COL8	8 column bits
  0x1	COL9	9 column bits
  0x2	COL10	10 column bits
  0x3	COL11	11 column bits

• NR: Number of Row Bits

  Value	Name	Description
  0x0	ROW11	11 row bits
  0x1	ROW12	12 row bits
  0x2	ROW13	13 row bits

• NB: Number of Banks

  Value	Name	Description
  0	BANK2	2 banks
  1	BANK4	4 banks

• CAS: CAS Latency

  Value	Name	Description
  0x1	LATENCY1	1 cycle CAS latency
  0x2	LATENCY2	2 cycle CAS latency
  0x3	LATENCY3	3 cycle CAS latency

• DBW: Data Bus Width

-

• TWR: Write Recovery Delay

-

• TRC_TRFC: Row Cycle Delay and Row Refresh Cycle

-

• TRP: Row Precharge Delay

-

• TRCD: Row to Column Delay

-

• TRAS: Active to Precharge Delay

-

• TXSR: Exit Self Refresh to Active Delay

-

SDRAMC SDRAMC Low Power Register

Name: SDRAMC_LPR

Access: read-write

Address: 0x400E0210

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	TIMEOUT		DS		TCSR
7	6	5	4	3	2	1	0
-	PASR			-	-	LPCB

• LPCB: Low-power Configuration Bits

  Value	Name	Description
  0x0	DISABLED	Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
  0x1	SELF_REFRESH	The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access.
  0x2	POWER_DOWN	The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access.
  0x3	DEEP_POWER_DOWN	The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.

• PASR: Partial Array Self-refresh (only for low-power SDRAM)

-

• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)

-

• DS: Drive Strength (only for low-power SDRAM)

-

• TIMEOUT: Time to define when low-power mode is enable

  Value	Name	Description
  0x0	LP_LAST_XFER	The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
  0x1	LP_LAST_XFER_64	The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
  0x2	LP_LAST_XFER_128	The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.

SDRAMC SDRAMC Interrupt Enable Register

Name: SDRAMC_IER

Access: write-only

Address: 0x400E0214

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RES

• RES: Refresh Error Status

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the refresh error interrupt.

SDRAMC SDRAMC Interrupt Disable Register

Name: SDRAMC_IDR

Access: write-only

Address: 0x400E0218

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RES

• RES: Refresh Error Status

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the refresh error interrupt.

SDRAMC SDRAMC Interrupt Mask Register

Name: SDRAMC_IMR

Access: read-only

Address: 0x400E021C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RES

• RES: Refresh Error Status

  Value	Name	Description
  0	-	The refresh error interrupt is disabled.
  1	-	The refresh error interrupt is enabled.

SDRAMC SDRAMC Interrupt Status Register

Name: SDRAMC_ISR

Access: read-only

Address: 0x400E0220

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RES

• RES: Refresh Error Status

  Value	Name	Description
  0	-	No refresh error has been detected since the register was last read.
  1	-	A refresh error has been detected since the register was last read.

SDRAMC SDRAMC Memory Device Register

Name: SDRAMC_MDR

Access: read-write

Address: 0x400E0224

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	MD

• MD: Memory Device Type

  Value	Name	Description
  0x0	SDRAM	SDRAM
  0x1	LPSDRAM	Low-power SDRAM

SDRAMC SDRAMC Configuration Register 1

Name: SDRAMC_CR1

Access: read-write

Address: 0x400E0228

31	30	29	28	27	26	25	24
TXSR				TRAS
23	22	21	20	19	18	17	16
TRCD				TRP
15	14	13	12	11	10	9	8
TRC_TRFC				TWR
7	6	5	4	3	2	1	0
DBW	CAS		NB	NR		NC

• NC: Number of Column Bits

  Value	Name	Description
  0x0	COL8	8 column bits
  0x1	COL9	9 column bits
  0x2	COL10	10 column bits
  0x3	COL11	11 column bits

• NR: Number of Row Bits

  Value	Name	Description
  0x0	ROW11	11 row bits
  0x1	ROW12	12 row bits
  0x2	ROW13	13 row bits

• NB: Number of Banks

  Value	Name	Description
  0	BANK2	2 banks
  1	BANK4	4 banks

• CAS: CAS Latency

  Value	Name	Description
  0x1	LATENCY1	1 cycle CAS latency
  0x2	LATENCY2	2 cycle CAS latency
  0x3	LATENCY3	3 cycle CAS latency

• DBW: Data Bus Width

-

• TWR: Write Recovery Delay

-

• TRC_TRFC: Row Cycle Delay and Row Refresh Cycle

-

• TRP: Row Precharge Delay

-

• TRCD: Row to Column Delay

-

• TRAS: Active to Precharge Delay

-

• TXSR: Exit Self Refresh to Active Delay

-

SDRAMC SDRAMC OCMS Register 1

Name: SDRAMC_OCMS

Access: read-write

Address: 0x400E022C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	SDR_SE

• SDR_SE: SDRAM Memory Controller Scrambling Enable

  Value	Name	Description
  0	-	Disable "Off Chip" Scrambling for SDR-SDRAM access.
  1	-	Enable "Off Chip" Scrambling for SDR-SDRAM access.