SAM3XA RSTC

Reset Controller (RSTC) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x400E1A00	Control Register	RSTC_CR	write-only	-
0x400E1A04	Status Register	RSTC_SR	read-only	0x00000000
0x400E1A08	Mode Register	RSTC_MR	read-write	0x00000001

Register Fields

RSTC Control Register

Name: RSTC_CR

Access: write-only

Address: 0x400E1A00

31	30	29	28	27	26	25	24
KEY
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	EXTRST	PERRST	-	PROCRST

• PROCRST: Processor Reset

  Value	Name	Description
  0	-	No effect.
  1	-	If KEY is correct, resets the processor.

• PERRST: Peripheral Reset

  Value	Name	Description
  0	-	No effect.
  1	-	If KEY is correct, resets the peripherals.

• EXTRST: External Reset

  Value	Name	Description
  0	-	No effect.
  1	-	If KEY is correct, asserts the NRST pin.

• KEY: Password

-

RSTC Status Register

Name: RSTC_SR

Access: read-only

Address: 0x400E1A04

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	SRCMP	NRSTL
15	14	13	12	11	10	9	8
-	-	-	-	-	RSTTYP
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	URSTS

• URSTS: User Reset Status

  Value	Name	Description
  0	-	No high-to-low edge on NRST happened since the last read of RSTC_SR.
  1	-	At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

-

• NRSTL: NRST Pin Level

-

• SRCMP: Software Reset Command in Progress

  Value	Name	Description
  0	-	No software command is being performed by the reset controller. The reset controller is ready for a software command.
  1	-	A software reset command is being performed by the reset controller. The reset controller is busy.

RSTC Mode Register

Name: RSTC_MR

Access: read-write

Address: 0x400E1A08

31	30	29	28	27	26	25	24
KEY
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	ERSTL
7	6	5	4	3	2	1	0
-	-	-	URSTIEN	-	-	-	URSTEN

• URSTEN: User Reset Enable

  Value	Name	Description
  0	-	The detection of a low level on the pin NRST does not generate a User Reset.
  1	-	The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

  Value	Name	Description
  0	-	USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
  1	-	USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• ERSTL: External Reset Length

-

• KEY: Password

-