SAM3XA PWM

Pulse Width Modulation Controller (PWM) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x40094000	PWM Clock Register	PWM_CLK	read-write	0x00000000
0x40094004	PWM Enable Register	PWM_ENA	write-only	-
0x40094008	PWM Disable Register	PWM_DIS	write-only	-
0x4009400C	PWM Status Register	PWM_SR	read-only	0x00000000
0x40094010	PWM Interrupt Enable Register 1	PWM_IER1	write-only	-
0x40094014	PWM Interrupt Disable Register 1	PWM_IDR1	write-only	-
0x40094018	PWM Interrupt Mask Register 1	PWM_IMR1	read-only	0x00000000
0x4009401C	PWM Interrupt Status Register 1	PWM_ISR1	read-only	0x00000000
0x40094020	PWM Sync Channels Mode Register	PWM_SCM	read-write	0x00000000
0x40094028	PWM Sync Channels Update Control Register	PWM_SCUC	read-write	0x00000000
0x4009402C	PWM Sync Channels Update Period Register	PWM_SCUP	read-write	0x00000000
0x40094030	PWM Sync Channels Update Period Update Register	PWM_SCUPUPD	write-only	0x00000000
0x40094034	PWM Interrupt Enable Register 2	PWM_IER2	write-only	-
0x40094038	PWM Interrupt Disable Register 2	PWM_IDR2	write-only	-
0x4009403C	PWM Interrupt Mask Register 2	PWM_IMR2	read-only	0x00000000
0x40094040	PWM Interrupt Status Register 2	PWM_ISR2	read-only	0x00000000
0x40094044	PWM Output Override Value Register	PWM_OOV	read-write	0x00000000
0x40094048	PWM Output Selection Register	PWM_OS	read-write	0x00000000
0x4009404C	PWM Output Selection Set Register	PWM_OSS	write-only	-
0x40094050	PWM Output Selection Clear Register	PWM_OSC	write-only	-
0x40094054	PWM Output Selection Set Update Register	PWM_OSSUPD	write-only	-
0x40094058	PWM Output Selection Clear Update Register	PWM_OSCUPD	write-only	-
0x4009405C	PWM Fault Mode Register	PWM_FMR	read-write	0x00000000
0x40094060	PWM Fault Status Register	PWM_FSR	read-only	0x00000000
0x40094064	PWM Fault Clear Register	PWM_FCR	write-only	-
0x40094068	PWM Fault Protection Value Register	PWM_FPV	read-write	0x00000000
0x4009406C	PWM Fault Protection Enable Register 1	PWM_FPE1	read-write	0x00000000
0x40094070	PWM Fault Protection Enable Register 2	PWM_FPE2	read-write	0x00000000
0x4009407C	PWM Event Line 0 Mode Register	PWM_ELMR[2]	read-write	0x0
0x400940B0	PWM Stepper Motor Mode Register	PWM_SMMR	read-write	0x00000000
0x400940E4	PWM Write Protect Control Register	PWM_WPCR	write-only	-
0x400940E8	PWM Write Protect Status Register	PWM_WPSR	read-only	0x00000000
0x40094130	PWM Comparison 0 Value Register	PWM_CMPV0	read-write	0x00000000
0x40094134	PWM Comparison 0 Value Update Register	PWM_CMPVUPD0	write-only	-
0x40094138	PWM Comparison 0 Mode Register	PWM_CMPM0	read-write	0x00000000
0x4009413C	PWM Comparison 0 Mode Update Register	PWM_CMPMUPD0	write-only	-
0x40094140	PWM Comparison 1 Value Register	PWM_CMPV1	read-write	0x00000000
0x40094144	PWM Comparison 1 Value Update Register	PWM_CMPVUPD1	write-only	-
0x40094148	PWM Comparison 1 Mode Register	PWM_CMPM1	read-write	0x00000000
0x4009414C	PWM Comparison 1 Mode Update Register	PWM_CMPMUPD1	write-only	-
0x40094150	PWM Comparison 2 Value Register	PWM_CMPV2	read-write	0x00000000
0x40094154	PWM Comparison 2 Value Update Register	PWM_CMPVUPD2	write-only	-
0x40094158	PWM Comparison 2 Mode Register	PWM_CMPM2	read-write	0x00000000
0x4009415C	PWM Comparison 2 Mode Update Register	PWM_CMPMUPD2	write-only	-
0x40094160	PWM Comparison 3 Value Register	PWM_CMPV3	read-write	0x00000000
0x40094164	PWM Comparison 3 Value Update Register	PWM_CMPVUPD3	write-only	-
0x40094168	PWM Comparison 3 Mode Register	PWM_CMPM3	read-write	0x00000000
0x4009416C	PWM Comparison 3 Mode Update Register	PWM_CMPMUPD3	write-only	-
0x40094170	PWM Comparison 4 Value Register	PWM_CMPV4	read-write	0x00000000
0x40094174	PWM Comparison 4 Value Update Register	PWM_CMPVUPD4	write-only	-
0x40094178	PWM Comparison 4 Mode Register	PWM_CMPM4	read-write	0x00000000
0x4009417C	PWM Comparison 4 Mode Update Register	PWM_CMPMUPD4	write-only	-
0x40094180	PWM Comparison 5 Value Register	PWM_CMPV5	read-write	0x00000000
0x40094184	PWM Comparison 5 Value Update Register	PWM_CMPVUPD5	write-only	-
0x40094188	PWM Comparison 5 Mode Register	PWM_CMPM5	read-write	0x00000000
0x4009418C	PWM Comparison 5 Mode Update Register	PWM_CMPMUPD5	write-only	-
0x40094190	PWM Comparison 6 Value Register	PWM_CMPV6	read-write	0x00000000
0x40094194	PWM Comparison 6 Value Update Register	PWM_CMPVUPD6	write-only	-
0x40094198	PWM Comparison 6 Mode Register	PWM_CMPM6	read-write	0x00000000
0x4009419C	PWM Comparison 6 Mode Update Register	PWM_CMPMUPD6	write-only	-
0x400941A0	PWM Comparison 7 Value Register	PWM_CMPV7	read-write	0x00000000
0x400941A4	PWM Comparison 7 Value Update Register	PWM_CMPVUPD7	write-only	-
0x400941A8	PWM Comparison 7 Mode Register	PWM_CMPM7	read-write	0x00000000
0x400941AC	PWM Comparison 7 Mode Update Register	PWM_CMPMUPD7	write-only	-
0x40094200	PWM Channel Mode Register (ch_num = 0)	PWM_CMR0	read-write	0x00000000
0x40094204	PWM Channel Duty Cycle Register (ch_num = 0)	PWM_CDTY0	read-write	0x00000000
0x40094208	PWM Channel Duty Cycle Update Register (ch_num = 0)	PWM_CDTYUPD0	write-only	-
0x4009420C	PWM Channel Period Register (ch_num = 0)	PWM_CPRD0	read-write	0x00000000
0x40094210	PWM Channel Period Update Register (ch_num = 0)	PWM_CPRDUPD0	write-only	-
0x40094214	PWM Channel Counter Register (ch_num = 0)	PWM_CCNT0	read-only	0x00000000
0x40094218	PWM Channel Dead Time Register (ch_num = 0)	PWM_DT0	read-write	0x00000000
0x4009421C	PWM Channel Dead Time Update Register (ch_num = 0)	PWM_DTUPD0	write-only	-
0x40094220	PWM Channel Mode Register (ch_num = 1)	PWM_CMR1	read-write	0x00000000
0x40094224	PWM Channel Duty Cycle Register (ch_num = 1)	PWM_CDTY1	read-write	0x00000000
0x40094228	PWM Channel Duty Cycle Update Register (ch_num = 1)	PWM_CDTYUPD1	write-only	-
0x4009422C	PWM Channel Period Register (ch_num = 1)	PWM_CPRD1	read-write	0x00000000
0x40094230	PWM Channel Period Update Register (ch_num = 1)	PWM_CPRDUPD1	write-only	-
0x40094234	PWM Channel Counter Register (ch_num = 1)	PWM_CCNT1	read-only	0x00000000
0x40094238	PWM Channel Dead Time Register (ch_num = 1)	PWM_DT1	read-write	0x00000000
0x4009423C	PWM Channel Dead Time Update Register (ch_num = 1)	PWM_DTUPD1	write-only	-
0x40094240	PWM Channel Mode Register (ch_num = 2)	PWM_CMR2	read-write	0x00000000
0x40094244	PWM Channel Duty Cycle Register (ch_num = 2)	PWM_CDTY2	read-write	0x00000000
0x40094248	PWM Channel Duty Cycle Update Register (ch_num = 2)	PWM_CDTYUPD2	write-only	-
0x4009424C	PWM Channel Period Register (ch_num = 2)	PWM_CPRD2	read-write	0x00000000
0x40094250	PWM Channel Period Update Register (ch_num = 2)	PWM_CPRDUPD2	write-only	-
0x40094254	PWM Channel Counter Register (ch_num = 2)	PWM_CCNT2	read-only	0x00000000
0x40094258	PWM Channel Dead Time Register (ch_num = 2)	PWM_DT2	read-write	0x00000000
0x4009425C	PWM Channel Dead Time Update Register (ch_num = 2)	PWM_DTUPD2	write-only	-
0x40094260	PWM Channel Mode Register (ch_num = 3)	PWM_CMR3	read-write	0x00000000
0x40094264	PWM Channel Duty Cycle Register (ch_num = 3)	PWM_CDTY3	read-write	0x00000000
0x40094268	PWM Channel Duty Cycle Update Register (ch_num = 3)	PWM_CDTYUPD3	write-only	-
0x4009426C	PWM Channel Period Register (ch_num = 3)	PWM_CPRD3	read-write	0x00000000
0x40094270	PWM Channel Period Update Register (ch_num = 3)	PWM_CPRDUPD3	write-only	-
0x40094274	PWM Channel Counter Register (ch_num = 3)	PWM_CCNT3	read-only	0x00000000
0x40094278	PWM Channel Dead Time Register (ch_num = 3)	PWM_DT3	read-write	0x00000000
0x4009427C	PWM Channel Dead Time Update Register (ch_num = 3)	PWM_DTUPD3	write-only	-
0x40094280	PWM Channel Mode Register (ch_num = 4)	PWM_CMR4	read-write	0x00000000
0x40094284	PWM Channel Duty Cycle Register (ch_num = 4)	PWM_CDTY4	read-write	0x00000000
0x40094288	PWM Channel Duty Cycle Update Register (ch_num = 4)	PWM_CDTYUPD4	write-only	-
0x4009428C	PWM Channel Period Register (ch_num = 4)	PWM_CPRD4	read-write	0x00000000
0x40094290	PWM Channel Period Update Register (ch_num = 4)	PWM_CPRDUPD4	write-only	-
0x40094294	PWM Channel Counter Register (ch_num = 4)	PWM_CCNT4	read-only	0x00000000
0x40094298	PWM Channel Dead Time Register (ch_num = 4)	PWM_DT4	read-write	0x00000000
0x4009429C	PWM Channel Dead Time Update Register (ch_num = 4)	PWM_DTUPD4	write-only	-
0x400942A0	PWM Channel Mode Register (ch_num = 5)	PWM_CMR5	read-write	0x00000000
0x400942A4	PWM Channel Duty Cycle Register (ch_num = 5)	PWM_CDTY5	read-write	0x00000000
0x400942A8	PWM Channel Duty Cycle Update Register (ch_num = 5)	PWM_CDTYUPD5	write-only	-
0x400942AC	PWM Channel Period Register (ch_num = 5)	PWM_CPRD5	read-write	0x00000000
0x400942B0	PWM Channel Period Update Register (ch_num = 5)	PWM_CPRDUPD5	write-only	-
0x400942B4	PWM Channel Counter Register (ch_num = 5)	PWM_CCNT5	read-only	0x00000000
0x400942B8	PWM Channel Dead Time Register (ch_num = 5)	PWM_DT5	read-write	0x00000000
0x400942BC	PWM Channel Dead Time Update Register (ch_num = 5)	PWM_DTUPD5	write-only	-
0x400942C0	PWM Channel Mode Register (ch_num = 6)	PWM_CMR6	read-write	0x00000000
0x400942C4	PWM Channel Duty Cycle Register (ch_num = 6)	PWM_CDTY6	read-write	0x00000000
0x400942C8	PWM Channel Duty Cycle Update Register (ch_num = 6)	PWM_CDTYUPD6	write-only	-
0x400942CC	PWM Channel Period Register (ch_num = 6)	PWM_CPRD6	read-write	0x00000000
0x400942D0	PWM Channel Period Update Register (ch_num = 6)	PWM_CPRDUPD6	write-only	-
0x400942D4	PWM Channel Counter Register (ch_num = 6)	PWM_CCNT6	read-only	0x00000000
0x400942D8	PWM Channel Dead Time Register (ch_num = 6)	PWM_DT6	read-write	0x00000000
0x400942DC	PWM Channel Dead Time Update Register (ch_num = 6)	PWM_DTUPD6	write-only	-
0x400942E0	PWM Channel Mode Register (ch_num = 7)	PWM_CMR7	read-write	0x00000000
0x400942E4	PWM Channel Duty Cycle Register (ch_num = 7)	PWM_CDTY7	read-write	0x00000000
0x400942E8	PWM Channel Duty Cycle Update Register (ch_num = 7)	PWM_CDTYUPD7	write-only	-
0x400942EC	PWM Channel Period Register (ch_num = 7)	PWM_CPRD7	read-write	0x00000000
0x400942F0	PWM Channel Period Update Register (ch_num = 7)	PWM_CPRDUPD7	write-only	-
0x400942F4	PWM Channel Counter Register (ch_num = 7)	PWM_CCNT7	read-only	0x00000000
0x400942F8	PWM Channel Dead Time Register (ch_num = 7)	PWM_DT7	read-write	0x00000000
0x400942FC	PWM Channel Dead Time Update Register (ch_num = 7)	PWM_DTUPD7	write-only	-
0x40094108	Transmit Pointer Register	PWM_TPR	read-write	0x00000000
0x4009410C	Transmit Counter Register	PWM_TCR	read-write	0x00000000
0x40094118	Transmit Next Pointer Register	PWM_TNPR	read-write	0x00000000
0x4009411C	Transmit Next Counter Register	PWM_TNCR	read-write	0x00000000
0x40094120	Transfer Control Register	PWM_PTCR	write-only	0x00000000
0x40094124	Transfer Status Register	PWM_PTSR	read-only	0x00000000

Register Fields

PWM PWM Clock Register

Name: PWM_CLK

Access: read-write

Address: 0x40094000

31	30	29	28	27	26	25	24
-	-	-	-	PREB
23	22	21	20	19	18	17	16
DIVB
15	14	13	12	11	10	9	8
-	-	-	-	PREA
7	6	5	4	3	2	1	0
DIVA

• DIVA: CLKA, CLKB Divide Factor

  Value	Name	Description
  0	-	CLKA, CLKB clock is turned off
  1	-	CLKA, CLKB clock is clock selected by PREA, PREB

• PREA: CLKA, CLKB Source Clock Selection

  Value	Name	Description
  0x0	-	MCK
  0x1	-	MCK/2
  0x2	-	MCK/4
  0x3	-	MCK/8
  0x4	-	MCK/16
  0x5	-	MCK/32
  0x6	-	MCK/64
  0x7	-	MCK/128
  0x8	-	MCK/256
  0x9	-	MCK/512
  0xA	-	MCK/1024

• DIVB: CLKA, CLKB Divide Factor

  Value	Name	Description
  0	-	CLKA, CLKB clock is turned off
  1	-	CLKA, CLKB clock is clock selected by PREA, PREB

• PREB: CLKA, CLKB Source Clock Selection

  Value	Name	Description
  0x0	-	MCK
  0x1	-	MCK/2
  0x2	-	MCK/4
  0x3	-	MCK/8
  0x4	-	MCK/16
  0x5	-	MCK/32
  0x6	-	MCK/64
  0x7	-	MCK/128
  0x8	-	MCK/256
  0x9	-	MCK/512
  0xA	-	MCK/1024

PWM PWM Enable Register

Name: PWM_ENA

Access: write-only

Address: 0x40094004

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID1: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID2: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID3: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID4: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID5: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID6: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

• CHID7: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Enable PWM output for channel x.

PWM PWM Disable Register

Name: PWM_DIS

Access: write-only

Address: 0x40094008

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID1: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID2: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID3: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID4: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID5: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID6: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

• CHID7: Channel ID

  Value	Name	Description
  0	-	No effect.
  1	-	Disable PWM output for channel x.

PWM PWM Status Register

Name: PWM_SR

Access: read-only

Address: 0x4009400C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID1: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID2: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID3: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID4: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID5: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID6: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

• CHID7: Channel ID

  Value	Name	Description
  0	-	PWM output for channel x is disabled.
  1	-	PWM output for channel x is enabled.

PWM PWM Interrupt Enable Register 1

Name: PWM_IER1

Access: write-only

Address: 0x40094010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FCHID7	FCHID6	FCHID5	FCHID4	FCHID3	FCHID2	FCHID1	FCHID0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Counter Event on Channel 0 Interrupt Enable

-

• CHID1: Counter Event on Channel 1 Interrupt Enable

-

• CHID2: Counter Event on Channel 2 Interrupt Enable

-

• CHID3: Counter Event on Channel 3 Interrupt Enable

-

• CHID4: Counter Event on Channel 4 Interrupt Enable

-

• CHID5: Counter Event on Channel 5 Interrupt Enable

-

• CHID6: Counter Event on Channel 6 Interrupt Enable

-

• CHID7: Counter Event on Channel 7 Interrupt Enable

-

• FCHID0: Fault Protection Trigger on Channel 0 Interrupt Enable

-

• FCHID1: Fault Protection Trigger on Channel 1 Interrupt Enable

-

• FCHID2: Fault Protection Trigger on Channel 2 Interrupt Enable

-

• FCHID3: Fault Protection Trigger on Channel 3 Interrupt Enable

-

• FCHID4: Fault Protection Trigger on Channel 4 Interrupt Enable

-

• FCHID5: Fault Protection Trigger on Channel 5 Interrupt Enable

-

• FCHID6: Fault Protection Trigger on Channel 6 Interrupt Enable

-

• FCHID7: Fault Protection Trigger on Channel 7 Interrupt Enable

-

PWM PWM Interrupt Disable Register 1

Name: PWM_IDR1

Access: write-only

Address: 0x40094014

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FCHID7	FCHID6	FCHID5	FCHID4	FCHID3	FCHID2	FCHID1	FCHID0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Counter Event on Channel 0 Interrupt Disable

-

• CHID1: Counter Event on Channel 1 Interrupt Disable

-

• CHID2: Counter Event on Channel 2 Interrupt Disable

-

• CHID3: Counter Event on Channel 3 Interrupt Disable

-

• CHID4: Counter Event on Channel 4 Interrupt Disable

-

• CHID5: Counter Event on Channel 5 Interrupt Disable

-

• CHID6: Counter Event on Channel 6 Interrupt Disable

-

• CHID7: Counter Event on Channel 7 Interrupt Disable

-

• FCHID0: Fault Protection Trigger on Channel 0 Interrupt Disable

-

• FCHID1: Fault Protection Trigger on Channel 1 Interrupt Disable

-

• FCHID2: Fault Protection Trigger on Channel 2 Interrupt Disable

-

• FCHID3: Fault Protection Trigger on Channel 3 Interrupt Disable

-

• FCHID4: Fault Protection Trigger on Channel 4 Interrupt Disable

-

• FCHID5: Fault Protection Trigger on Channel 5 Interrupt Disable

-

• FCHID6: Fault Protection Trigger on Channel 6 Interrupt Disable

-

• FCHID7: Fault Protection Trigger on Channel 7 Interrupt Disable

-

PWM PWM Interrupt Mask Register 1

Name: PWM_IMR1

Access: read-only

Address: 0x40094018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FCHID7	FCHID6	FCHID5	FCHID4	FCHID3	FCHID2	FCHID1	FCHID0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Counter Event on Channel 0 Interrupt Mask

-

• CHID1: Counter Event on Channel 1 Interrupt Mask

-

• CHID2: Counter Event on Channel 2 Interrupt Mask

-

• CHID3: Counter Event on Channel 3 Interrupt Mask

-

• CHID4: Counter Event on Channel 4 Interrupt Mask

-

• CHID5: Counter Event on Channel 5 Interrupt Mask

-

• CHID6: Counter Event on Channel 6 Interrupt Mask

-

• CHID7: Counter Event on Channel 7 Interrupt Mask

-

• FCHID0: Fault Protection Trigger on Channel 0 Interrupt Mask

-

• FCHID1: Fault Protection Trigger on Channel 1 Interrupt Mask

-

• FCHID2: Fault Protection Trigger on Channel 2 Interrupt Mask

-

• FCHID3: Fault Protection Trigger on Channel 3 Interrupt Mask

-

• FCHID4: Fault Protection Trigger on Channel 4 Interrupt Mask

-

• FCHID5: Fault Protection Trigger on Channel 5 Interrupt Mask

-

• FCHID6: Fault Protection Trigger on Channel 6 Interrupt Mask

-

• FCHID7: Fault Protection Trigger on Channel 7 Interrupt Mask

-

PWM PWM Interrupt Status Register 1

Name: PWM_ISR1

Access: read-only

Address: 0x4009401C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FCHID7	FCHID6	FCHID5	FCHID4	FCHID3	FCHID2	FCHID1	FCHID0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CHID7	CHID6	CHID5	CHID4	CHID3	CHID2	CHID1	CHID0

• CHID0: Counter Event on Channel 0

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID1: Counter Event on Channel 1

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID2: Counter Event on Channel 2

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID3: Counter Event on Channel 3

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID4: Counter Event on Channel 4

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID5: Counter Event on Channel 5

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID6: Counter Event on Channel 6

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• CHID7: Counter Event on Channel 7

  Value	Name	Description
  0	-	No new counter event has occurred since the last read of the PWM_ISR1 register.
  1	-	At least one counter event has occurred since the last read of the PWM_ISR1 register.

• FCHID0: Fault Protection Trigger on Channel 0

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID1: Fault Protection Trigger on Channel 1

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID2: Fault Protection Trigger on Channel 2

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID3: Fault Protection Trigger on Channel 3

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID4: Fault Protection Trigger on Channel 4

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID5: Fault Protection Trigger on Channel 5

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID6: Fault Protection Trigger on Channel 6

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

• FCHID7: Fault Protection Trigger on Channel 7

  Value	Name	Description
  0	-	No new trigger of the fault protection since the last read of the PWM_ISR1 register.
  1	-	At least one trigger of the fault protection since the last read of the PWM_ISR1 register.

PWM PWM Sync Channels Mode Register

Name: PWM_SCM

Access: read-write

Address: 0x40094020

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
PTRCS			PTRM	-	-	UPDM
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
SYNC7	SYNC6	SYNC5	SYNC4	SYNC3	SYNC2	SYNC1	SYNC0

• SYNC0: Synchronous Channel 0

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC1: Synchronous Channel 1

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC2: Synchronous Channel 2

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC3: Synchronous Channel 3

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC4: Synchronous Channel 4

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC5: Synchronous Channel 5

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC6: Synchronous Channel 6

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• SYNC7: Synchronous Channel 7

  Value	Name	Description
  0	-	Channel x is not a synchronous channel.
  1	-	Channel x is a synchronous channel.

• UPDM: Synchronous Channels Update Mode

  Value	Name	Description
  0x0	MODE0	Manual write of double buffer registers and manual update of synchronous channels
  0x1	MODE1	Manual write of double buffer registers and automatic update of synchronous channels
  0x2	MODE2	Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels

• PTRM: PDC Transfer Request Mode

  Value	Name	Description
  0x1	-	The WRDY flag in "PWM Interrupt Status Register 2" on page 60 and the PDC transfer request are set to 1 as soon as the selected comparison matches.
  0xA	-	The WRDY flag in "PWM Interrupt Status Register 2" on page 60 is set to 1 as soon as the update period is elapsed, the PDC transfer request is never set to 1.
  0x14	-	The WRDY flag in "PWM Interrupt Status Register 2" on page 60 and the PDC transfer request are set to 1 as soon as the update period is elapsed.

• PTRCS: PDC Transfer Request Comparison Selection

-

PWM PWM Sync Channels Update Control Register

Name: PWM_SCUC

Access: read-write

Address: 0x40094028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	UPDULOCK

• UPDULOCK: Synchronous Channels Update Unlock

  Value	Name	Description
  0	-	No effect
  1	-	If the UPDM field is set to "0" in "PWM Sync Channels Mode Register" on page 53, writing the UPDULOCK bit to "1" triggers the update of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next PWM period. If the field UPDM is set to "1" or "2", writing the UPDULOCK bit to "1" triggers only the update of the period value and of the dead-time values of synchronous channels.

PWM PWM Sync Channels Update Period Register

Name: PWM_SCUP

Access: read-write

Address: 0x4009402C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
UPRCNT				UPR

• UPR: Update Period

-

• UPRCNT: Update Period Counter

-

PWM PWM Sync Channels Update Period Update Register

Name: PWM_SCUPUPD

Access: write-only

Address: 0x40094030

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	UPRUPD

• UPRUPD: Update Period Update

-

PWM PWM Interrupt Enable Register 2

Name: PWM_IER2

Access: write-only

Address: 0x40094034

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CMPU7	CMPU6	CMPU5	CMPU4	CMPU3	CMPU2	CMPU1	CMPU0
15	14	13	12	11	10	9	8
CMPM7	CMPM6	CMPM5	CMPM4	CMPM3	CMPM2	CMPM1	CMPM0
7	6	5	4	3	2	1	0
-	-	-	-	UNRE	TXBUFE	ENDTX	WRDY

• WRDY: Write Ready for Synchronous Channels Update Interrupt Enable

-

• ENDTX: PDC End of TX Buffer Interrupt Enable

-

• TXBUFE: PDC TX Buffer Empty Interrupt Enable

-

• UNRE: Synchronous Channels Update Underrun Error Interrupt Enable

-

• CMPM0: Comparison 0 Match Interrupt Enable

-

• CMPM1: Comparison 1 Match Interrupt Enable

-

• CMPM2: Comparison 2 Match Interrupt Enable

-

• CMPM3: Comparison 3 Match Interrupt Enable

-

• CMPM4: Comparison 4 Match Interrupt Enable

-

• CMPM5: Comparison 5 Match Interrupt Enable

-

• CMPM6: Comparison 6 Match Interrupt Enable

-

• CMPM7: Comparison 7 Match Interrupt Enable

-

• CMPU0: Comparison 0 Update Interrupt Enable

-

• CMPU1: Comparison 1 Update Interrupt Enable

-

• CMPU2: Comparison 2 Update Interrupt Enable

-

• CMPU3: Comparison 3 Update Interrupt Enable

-

• CMPU4: Comparison 4 Update Interrupt Enable

-

• CMPU5: Comparison 5 Update Interrupt Enable

-

• CMPU6: Comparison 6 Update Interrupt Enable

-

• CMPU7: Comparison 7 Update Interrupt Enable

-

PWM PWM Interrupt Disable Register 2

Name: PWM_IDR2

Access: write-only

Address: 0x40094038

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CMPU7	CMPU6	CMPU5	CMPU4	CMPU3	CMPU2	CMPU1	CMPU0
15	14	13	12	11	10	9	8
CMPM7	CMPM6	CMPM5	CMPM4	CMPM3	CMPM2	CMPM1	CMPM0
7	6	5	4	3	2	1	0
-	-	-	-	UNRE	TXBUFE	ENDTX	WRDY

• WRDY: Write Ready for Synchronous Channels Update Interrupt Disable

-

• ENDTX: PDC End of TX Buffer Interrupt Disable

-

• TXBUFE: PDC TX Buffer Empty Interrupt Disable

-

• UNRE: Synchronous Channels Update Underrun Error Interrupt Disable

-

• CMPM0: Comparison 0 Match Interrupt Disable

-

• CMPM1: Comparison 1 Match Interrupt Disable

-

• CMPM2: Comparison 2 Match Interrupt Disable

-

• CMPM3: Comparison 3 Match Interrupt Disable

-

• CMPM4: Comparison 4 Match Interrupt Disable

-

• CMPM5: Comparison 5 Match Interrupt Disable

-

• CMPM6: Comparison 6 Match Interrupt Disable

-

• CMPM7: Comparison 7 Match Interrupt Disable

-

• CMPU0: Comparison 0 Update Interrupt Disable

-

• CMPU1: Comparison 1 Update Interrupt Disable

-

• CMPU2: Comparison 2 Update Interrupt Disable

-

• CMPU3: Comparison 3 Update Interrupt Disable

-

• CMPU4: Comparison 4 Update Interrupt Disable

-

• CMPU5: Comparison 5 Update Interrupt Disable

-

• CMPU6: Comparison 6 Update Interrupt Disable

-

• CMPU7: Comparison 7 Update Interrupt Disable

-

PWM PWM Interrupt Mask Register 2

Name: PWM_IMR2

Access: read-only

Address: 0x4009403C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CMPU7	CMPU6	CMPU5	CMPU4	CMPU3	CMPU2	CMPU1	CMPU0
15	14	13	12	11	10	9	8
CMPM7	CMPM6	CMPM5	CMPM4	CMPM3	CMPM2	CMPM1	CMPM0
7	6	5	4	3	2	1	0
-	-	-	-	UNRE	TXBUFE	ENDTX	WRDY

• WRDY: Write Ready for Synchronous Channels Update Interrupt Mask

-

• ENDTX: PDC End of TX Buffer Interrupt Mask

-

• TXBUFE: PDC TX Buffer Empty Interrupt Mask

-

• UNRE: Synchronous Channels Update Underrun Error Interrupt Mask

-

• CMPM0: Comparison 0 Match Interrupt Mask

-

• CMPM1: Comparison 1 Match Interrupt Mask

-

• CMPM2: Comparison 2 Match Interrupt Mask

-

• CMPM3: Comparison 3 Match Interrupt Mask

-

• CMPM4: Comparison 4 Match Interrupt Mask

-

• CMPM5: Comparison 5 Match Interrupt Mask

-

• CMPM6: Comparison 6 Match Interrupt Mask

-

• CMPM7: Comparison 7 Match Interrupt Mask

-

• CMPU0: Comparison 0 Update Interrupt Mask

-

• CMPU1: Comparison 1 Update Interrupt Mask

-

• CMPU2: Comparison 2 Update Interrupt Mask

-

• CMPU3: Comparison 3 Update Interrupt Mask

-

• CMPU4: Comparison 4 Update Interrupt Mask

-

• CMPU5: Comparison 5 Update Interrupt Mask

-

• CMPU6: Comparison 6 Update Interrupt Mask

-

• CMPU7: Comparison 7 Update Interrupt Mask

-

PWM PWM Interrupt Status Register 2

Name: PWM_ISR2

Access: read-only

Address: 0x40094040

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CMPU7	CMPU6	CMPU5	CMPU4	CMPU3	CMPU2	CMPU1	CMPU0
15	14	13	12	11	10	9	8
CMPM7	CMPM6	CMPM5	CMPM4	CMPM3	CMPM2	CMPM1	CMPM0
7	6	5	4	3	2	1	0
-	-	-	-	UNRE	TXBUFE	ENDTX	WRDY

• WRDY: Write Ready for Synchronous Channels Update

  Value	Name	Description
  0	-	New duty-cycle and dead-time values for the synchronous channels cannot be written.
  1	-	New duty-cycle and dead-time values for the synchronous channels can be written.

• ENDTX: PDC End of TX Buffer

  Value	Name	Description
  0	-	The Transmit Counter register has not reached 0 since the last write of the PDC.
  1	-	The Transmit Counter register has reached 0 since the last write of the PDC.

• TXBUFE: PDC TX Buffer Empty

  Value	Name	Description
  0	-	PWM_TCR or PWM_TCNR has a value other than 0.
  1	-	Both PWM_TCR and PWM_TCNR have a value other than 0.

• UNRE: Synchronous Channels Update Underrun Error

  Value	Name	Description
  0	-	No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
  1	-	At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.

• CMPM0: Comparison 0 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM1: Comparison 1 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM2: Comparison 2 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM3: Comparison 3 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM4: Comparison 4 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM5: Comparison 5 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM6: Comparison 6 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPM7: Comparison 7 Match

  Value	Name	Description
  0	-	The comparison x has not matched since the last read of the PWM_ISR2 register.
  1	-	The comparison x has matched at least one time since the last read of the PWM_ISR2 register.

• CMPU0: Comparison 0 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU1: Comparison 1 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU2: Comparison 2 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU3: Comparison 3 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU4: Comparison 4 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU5: Comparison 5 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU6: Comparison 6 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

• CMPU7: Comparison 7 Update

  Value	Name	Description
  0	-	The comparison x has not been updated since the last read of the PWM_ISR2 register.
  1	-	The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.

PWM PWM Output Override Value Register

Name: PWM_OOV

Access: read-write

Address: 0x40094044

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OOVL7	OOVL6	OOVL5	OOVL4	OOVL3	OOVL2	OOVL1	OOVL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OOVH7	OOVH6	OOVH5	OOVH4	OOVH3	OOVH2	OOVH1	OOVH0

• OOVH0: Output Override Value for PWMH output of the channel 0

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH1: Output Override Value for PWMH output of the channel 1

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH2: Output Override Value for PWMH output of the channel 2

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH3: Output Override Value for PWMH output of the channel 3

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH4: Output Override Value for PWMH output of the channel 4

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH5: Output Override Value for PWMH output of the channel 5

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH6: Output Override Value for PWMH output of the channel 6

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVH7: Output Override Value for PWMH output of the channel 7

  Value	Name	Description
  0	-	Override value is 0 for PWMH output of channel x.
  1	-	Override value is 1 for PWMH output of channel x.

• OOVL0: Output Override Value for PWML output of the channel 0

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL1: Output Override Value for PWML output of the channel 1

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL2: Output Override Value for PWML output of the channel 2

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL3: Output Override Value for PWML output of the channel 3

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL4: Output Override Value for PWML output of the channel 4

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL5: Output Override Value for PWML output of the channel 5

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL6: Output Override Value for PWML output of the channel 6

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

• OOVL7: Output Override Value for PWML output of the channel 7

  Value	Name	Description
  0	-	Override value is 0 for PWML output of channel x.
  1	-	Override value is 1 for PWML output of channel x.

PWM PWM Output Selection Register

Name: PWM_OS

Access: read-write

Address: 0x40094048

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OSL7	OSL6	OSL5	OSL4	OSL3	OSL2	OSL1	OSL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OSH7	OSH6	OSH5	OSH4	OSH3	OSH2	OSH1	OSH0

• OSH0: Output Selection for PWMH output of the channel 0

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH1: Output Selection for PWMH output of the channel 1

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH2: Output Selection for PWMH output of the channel 2

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH3: Output Selection for PWMH output of the channel 3

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH4: Output Selection for PWMH output of the channel 4

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH5: Output Selection for PWMH output of the channel 5

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH6: Output Selection for PWMH output of the channel 6

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSH7: Output Selection for PWMH output of the channel 7

  Value	Name	Description
  0	-	Dead-time generator output DTOHx selected as PWMH output of channel x.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSL0: Output Selection for PWML output of the channel 0

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL1: Output Selection for PWML output of the channel 1

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL2: Output Selection for PWML output of the channel 2

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL3: Output Selection for PWML output of the channel 3

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL4: Output Selection for PWML output of the channel 4

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL5: Output Selection for PWML output of the channel 5

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL6: Output Selection for PWML output of the channel 6

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSL7: Output Selection for PWML output of the channel 7

  Value	Name	Description
  0	-	Dead-time generator output DTOLx selected as PWML output of channel x.
  1	-	Output override value OOVLx selected as PWML output of channel x.

PWM PWM Output Selection Set Register

Name: PWM_OSS

Access: write-only

Address: 0x4009404C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OSSL7	OSSL6	OSSL5	OSSL4	OSSL3	OSSL2	OSSL1	OSSL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OSSH7	OSSH6	OSSH5	OSSH4	OSSH3	OSSH2	OSSH1	OSSH0

• OSSH0: Output Selection Set for PWMH output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH1: Output Selection Set for PWMH output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH2: Output Selection Set for PWMH output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH3: Output Selection Set for PWMH output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH4: Output Selection Set for PWMH output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH5: Output Selection Set for PWMH output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH6: Output Selection Set for PWMH output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSH7: Output Selection Set for PWMH output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x.

• OSSL0: Output Selection Set for PWML output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL1: Output Selection Set for PWML output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL2: Output Selection Set for PWML output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL3: Output Selection Set for PWML output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL4: Output Selection Set for PWML output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL5: Output Selection Set for PWML output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL6: Output Selection Set for PWML output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

• OSSL7: Output Selection Set for PWML output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x.

PWM PWM Output Selection Clear Register

Name: PWM_OSC

Access: write-only

Address: 0x40094050

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OSCL7	OSCL6	OSCL5	OSCL4	OSCL3	OSCL2	OSCL1	OSCL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OSCH7	OSCH6	OSCH5	OSCH4	OSCH3	OSCH2	OSCH1	OSCH0

• OSCH0: Output Selection Clear for PWMH output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH1: Output Selection Clear for PWMH output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH2: Output Selection Clear for PWMH output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH3: Output Selection Clear for PWMH output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH4: Output Selection Clear for PWMH output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH5: Output Selection Clear for PWMH output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH6: Output Selection Clear for PWMH output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCH7: Output Selection Clear for PWMH output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x.

• OSCL0: Output Selection Clear for PWML output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL1: Output Selection Clear for PWML output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL2: Output Selection Clear for PWML output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL3: Output Selection Clear for PWML output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL4: Output Selection Clear for PWML output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL5: Output Selection Clear for PWML output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL6: Output Selection Clear for PWML output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

• OSCL7: Output Selection Clear for PWML output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x.

PWM PWM Output Selection Set Update Register

Name: PWM_OSSUPD

Access: write-only

Address: 0x40094054

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OSSUPL7	OSSUPL6	OSSUPL5	OSSUPL4	OSSUPL3	OSSUPL2	OSSUPL1	OSSUPL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OSSUPH7	OSSUPH6	OSSUPH5	OSSUPH4	OSSUPH3	OSSUPH2	OSSUPH1	OSSUPH0

• OSSUPH0: Output Selection Set for PWMH output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH1: Output Selection Set for PWMH output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH2: Output Selection Set for PWMH output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH3: Output Selection Set for PWMH output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH4: Output Selection Set for PWMH output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH5: Output Selection Set for PWMH output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH6: Output Selection Set for PWMH output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPH7: Output Selection Set for PWMH output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSSUPL0: Output Selection Set for PWML output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL1: Output Selection Set for PWML output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL2: Output Selection Set for PWML output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL3: Output Selection Set for PWML output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL4: Output Selection Set for PWML output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL5: Output Selection Set for PWML output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL6: Output Selection Set for PWML output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSSUPL7: Output Selection Set for PWML output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

PWM PWM Output Selection Clear Update Register

Name: PWM_OSCUPD

Access: write-only

Address: 0x40094058

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
OSCUPL7	OSCUPDL6	OSCUPL5	OSCUPL4	OSCUPL3	OSCUPL2	OSCUPL1	OSCUPL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
OSCUPH7	OSCUPH6	OSCUPH5	OSCUPH4	OSCUPH3	OSCUPH2	OSCUPH1	OSCUPH0

• OSCUPH0: Output Selection Clear for PWMH output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH1: Output Selection Clear for PWMH output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH2: Output Selection Clear for PWMH output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH3: Output Selection Clear for PWMH output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH4: Output Selection Clear for PWMH output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH5: Output Selection Clear for PWMH output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH6: Output Selection Clear for PWMH output of the channel 6

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPH7: Output Selection Clear for PWMH output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.

• OSCUPL0: Output Selection Clear for PWML output of the channel 0

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPL1: Output Selection Clear for PWML output of the channel 1

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPL2: Output Selection Clear for PWML output of the channel 2

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPL3: Output Selection Clear for PWML output of the channel 3

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPL4: Output Selection Clear for PWML output of the channel 4

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPL5: Output Selection Clear for PWML output of the channel 5

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

• OSCUPDL6

-

• OSCUPL7: Output Selection Clear for PWML output of the channel 7

  Value	Name	Description
  0	-	No effect.
  1	-	Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period.

PWM PWM Fault Mode Register

Name: PWM_FMR

Access: read-write

Address: 0x4009405C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FFIL
15	14	13	12	11	10	9	8
FMOD
7	6	5	4	3	2	1	0
FPOL

• FPOL: Fault Polarity (fault input bit varies from 0 to 5)

  Value	Name	Description
  0	-	The fault y becomes active when the fault input y is at 0.
  1	-	The fault y becomes active when the fault input y is at 1.

• FMOD: Fault Activation Mode (fault input bit varies from 0 to 5)

-

• FFIL: Fault Filtering (fault input bit varies from 0 to 5)

-

PWM PWM Fault Status Register

Name: PWM_FSR

Access: read-only

Address: 0x40094060

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
FS
7	6	5	4	3	2	1	0
FIV

• FIV: Fault Input Value (fault input bit varies from 0 to 5)

-

• FS: Fault Status (fault input bit varies from 0 to 5)

-

PWM PWM Fault Clear Register

Name: PWM_FCR

Access: write-only

Address: 0x40094064

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
FCLR

• FCLR: Fault Clear (fault input bit varies from 0 to 5)

-

PWM PWM Fault Protection Value Register

Name: PWM_FPV

Access: read-write

Address: 0x40094068

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
FPVL7	FPVL6	FPVL5	FPVL4	FPVL3	FPVL2	FPVL1	FPVL0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
FPVH7	FPVH6	FPVH5	FPVH4	FPVH3	FPVH2	FPVH1	FPVH0

• FPVH0: Fault Protection Value for PWMH output on channel 0

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH1: Fault Protection Value for PWMH output on channel 1

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH2: Fault Protection Value for PWMH output on channel 2

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH3: Fault Protection Value for PWMH output on channel 3

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH4: Fault Protection Value for PWMH output on channel 4

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH5: Fault Protection Value for PWMH output on channel 5

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH6: Fault Protection Value for PWMH output on channel 6

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVH7: Fault Protection Value for PWMH output on channel 7

  Value	Name	Description
  0	-	PWMH output of channel x is forced to 0 when fault occurs.
  1	-	PWMH output of channel x is forced to 1 when fault occurs.

• FPVL0: Fault Protection Value for PWML output on channel 0

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL1: Fault Protection Value for PWML output on channel 1

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL2: Fault Protection Value for PWML output on channel 2

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL3: Fault Protection Value for PWML output on channel 3

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL4: Fault Protection Value for PWML output on channel 4

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL5: Fault Protection Value for PWML output on channel 5

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL6: Fault Protection Value for PWML output on channel 6

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

• FPVL7: Fault Protection Value for PWML output on channel 7

  Value	Name	Description
  0	-	PWML output of channel x is forced to 0 when fault occurs.
  1	-	PWML output of channel x is forced to 1 when fault occurs.

PWM PWM Fault Protection Enable Register 1

Name: PWM_FPE1

Access: read-write

Address: 0x4009406C

31	30	29	28	27	26	25	24
FPE3
23	22	21	20	19	18	17	16
FPE2
15	14	13	12	11	10	9	8
FPE1
7	6	5	4	3	2	1	0
FPE0

• FPE0: Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5)

-

• FPE1: Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5)

-

• FPE2: Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5)

-

• FPE3: Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5)

-

PWM PWM Fault Protection Enable Register 2

Name: PWM_FPE2

Access: read-write

Address: 0x40094070

31	30	29	28	27	26	25	24
FPE7
23	22	21	20	19	18	17	16
FPE6
15	14	13	12	11	10	9	8
FPE5
7	6	5	4	3	2	1	0
FPE4

• FPE4: Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5)

-

• FPE5: Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5)

-

• FPE6: Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5)

-

• FPE7: Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5)

-

PWM PWM Event Line 0 Mode Register

Name: PWM_ELMR[0:1]

Access: read-write

Address: 0x4009407C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
CSEL7	CSEL6	CSEL5	CSEL4	CSEL3	CSEL2	CSEL1	CSEL0

• CSEL0: Comparison 0 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL1: Comparison 1 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL2: Comparison 2 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL3: Comparison 3 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL4: Comparison 4 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL5: Comparison 5 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL6: Comparison 6 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

• CSEL7: Comparison 7 Selection

  Value	Name	Description
  0	-	A pulse is not generated on the event line x when the comparison y matches.
  1	-	A pulse is generated on the event line x when the comparison y match.

PWM PWM Stepper Motor Mode Register

Name: PWM_SMMR

Access: read-write

Address: 0x400940B0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	DOWN3	DOWN2	DOWN1	DOWN0
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	GCEN3	GCEN2	GCEN1	GCEN0

• GCEN0: Gray Count ENable

  Value	Name	Description
  0	-	Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
  1	-	enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.

• GCEN1: Gray Count ENable

  Value	Name	Description
  0	-	Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
  1	-	enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.

• GCEN2: Gray Count ENable

  Value	Name	Description
  0	-	Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
  1	-	enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.

• GCEN3: Gray Count ENable

  Value	Name	Description
  0	-	Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
  1	-	enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.

• DOWN0: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

• DOWN1: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

• DOWN2: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

• DOWN3: DOWN Count

  Value	Name	Description
  0	-	Up counter.
  1	-	Down counter.

PWM PWM Write Protect Control Register

Name: PWM_WPCR

Access: write-only

Address: 0x400940E4

31	30	29	28	27	26	25	24
WPKEY
23	22	21	20	19	18	17	16
WPKEY
15	14	13	12	11	10	9	8
WPKEY
7	6	5	4	3	2	1	0
WPRG5	WPRG4	WPRG3	WPRG2	WPRG1	WPRG0	WPCMD

• WPCMD: Write Protect Command

  Value	Name	Description
  0x0	-	Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
  0x1	-	Enable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
  0x2	-	Enable the Write Protect HW of the register groups of which the bit WPRGx is at 1.
  0x3	-	No effect.

• WPRG0: Write Protect Register Group 0

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPRG1: Write Protect Register Group 1

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPRG2: Write Protect Register Group 2

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPRG3: Write Protect Register Group 3

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPRG4: Write Protect Register Group 4

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPRG5: Write Protect Register Group 5

  Value	Name	Description
  0	-	The WPCMD command has no effect on the register group x.
  1	-	The WPCMD command is applied to the register group x.

• WPKEY: Write Protect Key

-

PWM PWM Write Protect Status Register

Name: PWM_WPSR

Access: read-only

Address: 0x400940E8

31	30	29	28	27	26	25	24
WPVSRC
23	22	21	20	19	18	17	16
WPVSRC
15	14	13	12	11	10	9	8
-	-	WPHWS5	WPHWS4	WPHWS3	WPHWS2	WPHWS1	WPHWS0
7	6	5	4	3	2	1	0
WPVS	-	WPSWS5	WPSWS4	WPSWS3	WPSWS2	WPSWS1	WPSWS0

• WPSWS0: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPSWS1: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPSWS2: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPSWS3: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPSWS4: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPSWS5: Write Protect SW Status

  Value	Name	Description
  0	-	The Write Protect SW x of the register group x is disabled.
  1	-	The Write Protect SW x of the register group x is enabled.

• WPVS: Write Protect Violation Status

  Value	Name	Description
  0	-	No Write Protect violation has occurred since the last read of the PWM_WPSR register.
  1	-	At least one Write Protect violation has occurred since the last read of the PWM_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.

• WPHWS0: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPHWS1: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPHWS2: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPHWS3: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPHWS4: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPHWS5: Write Protect HW Status

  Value	Name	Description
  0	-	The Write Protect HW x of the register group x is disabled.
  1	-	The Write Protect HW x of the register group x is enabled.

• WPVSRC: Write Protect Violation Source

-

PWM PWM Comparison 0 Value Register

Name: PWM_CMPV0

Access: read-write

Address: 0x40094130

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 0 Value Update Register

Name: PWM_CMPVUPD0

Access: write-only

Address: 0x40094134

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 0 Mode Register

Name: PWM_CMPM0

Access: read-write

Address: 0x40094138

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 0 Mode Update Register

Name: PWM_CMPMUPD0

Access: write-only

Address: 0x4009413C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 1 Value Register

Name: PWM_CMPV1

Access: read-write

Address: 0x40094140

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 1 Value Update Register

Name: PWM_CMPVUPD1

Access: write-only

Address: 0x40094144

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 1 Mode Register

Name: PWM_CMPM1

Access: read-write

Address: 0x40094148

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 1 Mode Update Register

Name: PWM_CMPMUPD1

Access: write-only

Address: 0x4009414C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 2 Value Register

Name: PWM_CMPV2

Access: read-write

Address: 0x40094150

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 2 Value Update Register

Name: PWM_CMPVUPD2

Access: write-only

Address: 0x40094154

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 2 Mode Register

Name: PWM_CMPM2

Access: read-write

Address: 0x40094158

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 2 Mode Update Register

Name: PWM_CMPMUPD2

Access: write-only

Address: 0x4009415C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 3 Value Register

Name: PWM_CMPV3

Access: read-write

Address: 0x40094160

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 3 Value Update Register

Name: PWM_CMPVUPD3

Access: write-only

Address: 0x40094164

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 3 Mode Register

Name: PWM_CMPM3

Access: read-write

Address: 0x40094168

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 3 Mode Update Register

Name: PWM_CMPMUPD3

Access: write-only

Address: 0x4009416C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 4 Value Register

Name: PWM_CMPV4

Access: read-write

Address: 0x40094170

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 4 Value Update Register

Name: PWM_CMPVUPD4

Access: write-only

Address: 0x40094174

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 4 Mode Register

Name: PWM_CMPM4

Access: read-write

Address: 0x40094178

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 4 Mode Update Register

Name: PWM_CMPMUPD4

Access: write-only

Address: 0x4009417C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 5 Value Register

Name: PWM_CMPV5

Access: read-write

Address: 0x40094180

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 5 Value Update Register

Name: PWM_CMPVUPD5

Access: write-only

Address: 0x40094184

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 5 Mode Register

Name: PWM_CMPM5

Access: read-write

Address: 0x40094188

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 5 Mode Update Register

Name: PWM_CMPMUPD5

Access: write-only

Address: 0x4009418C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 6 Value Register

Name: PWM_CMPV6

Access: read-write

Address: 0x40094190

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 6 Value Update Register

Name: PWM_CMPVUPD6

Access: write-only

Address: 0x40094194

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 6 Mode Register

Name: PWM_CMPM6

Access: read-write

Address: 0x40094198

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 6 Mode Update Register

Name: PWM_CMPMUPD6

Access: write-only

Address: 0x4009419C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Comparison 7 Value Register

Name: PWM_CMPV7

Access: read-write

Address: 0x400941A0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVM
23	22	21	20	19	18	17	16
CV
15	14	13	12	11	10	9	8
CV
7	6	5	4	3	2	1	0
CV

• CV: Comparison x Value

-

• CVM: Comparison x Value Mode

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 7 Value Update Register

Name: PWM_CMPVUPD7

Access: write-only

Address: 0x400941A4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CVMUPD
23	22	21	20	19	18	17	16
CVUPD
15	14	13	12	11	10	9	8
CVUPD
7	6	5	4	3	2	1	0
CVUPD

• CVUPD: Comparison x Value Update

-

• CVMUPD: Comparison x Value Mode Update

  Value	Name	Description
  0	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing.
  1	-	The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing.

PWM PWM Comparison 7 Mode Register

Name: PWM_CMPM7

Access: read-write

Address: 0x400941A8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CUPRCNT				CUPR
15	14	13	12	11	10	9	8
CPRCNT				CPR
7	6	5	4	3	2	1	0
CTR				-	-	-	CEN

• CEN: Comparison x Enable

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTR: Comparison x Trigger

-

• CPR: Comparison x Period

-

• CPRCNT: Comparison x Period Counter

-

• CUPR: Comparison x Update Period

-

• CUPRCNT: Comparison x Update Period Counter

-

PWM PWM Comparison 7 Mode Update Register

Name: PWM_CMPMUPD7

Access: write-only

Address: 0x400941AC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	CUPRUPD
15	14	13	12	11	10	9	8
-	-	-	-	CPRUPD
7	6	5	4	3	2	1	0
CTRUPD				-	-	-	CENUPD

• CENUPD: Comparison x Enable Update

  Value	Name	Description
  0	-	The comparison x is disabled and can not match.
  1	-	The comparison x is enabled and can match.

• CTRUPD: Comparison x Trigger Update

-

• CPRUPD: Comparison x Period Update

-

• CUPRUPD: Comparison x Update Period Update

-

PWM PWM Channel Mode Register (ch_num = 0)

Name: PWM_CMR0

Access: read-write

Address: 0x40094200

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 0)

Name: PWM_CDTY0

Access: read-write

Address: 0x40094204

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 0)

Name: PWM_CDTYUPD0

Access: write-only

Address: 0x40094208

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 0)

Name: PWM_CPRD0

Access: read-write

Address: 0x4009420C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 0)

Name: PWM_CPRDUPD0

Access: write-only

Address: 0x40094210

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 0)

Name: PWM_CCNT0

Access: read-only

Address: 0x40094214

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 0)

Name: PWM_DT0

Access: read-write

Address: 0x40094218

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 0)

Name: PWM_DTUPD0

Access: write-only

Address: 0x4009421C

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 1)

Name: PWM_CMR1

Access: read-write

Address: 0x40094220

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 1)

Name: PWM_CDTY1

Access: read-write

Address: 0x40094224

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 1)

Name: PWM_CDTYUPD1

Access: write-only

Address: 0x40094228

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 1)

Name: PWM_CPRD1

Access: read-write

Address: 0x4009422C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 1)

Name: PWM_CPRDUPD1

Access: write-only

Address: 0x40094230

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 1)

Name: PWM_CCNT1

Access: read-only

Address: 0x40094234

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 1)

Name: PWM_DT1

Access: read-write

Address: 0x40094238

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 1)

Name: PWM_DTUPD1

Access: write-only

Address: 0x4009423C

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 2)

Name: PWM_CMR2

Access: read-write

Address: 0x40094240

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 2)

Name: PWM_CDTY2

Access: read-write

Address: 0x40094244

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 2)

Name: PWM_CDTYUPD2

Access: write-only

Address: 0x40094248

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 2)

Name: PWM_CPRD2

Access: read-write

Address: 0x4009424C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 2)

Name: PWM_CPRDUPD2

Access: write-only

Address: 0x40094250

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 2)

Name: PWM_CCNT2

Access: read-only

Address: 0x40094254

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 2)

Name: PWM_DT2

Access: read-write

Address: 0x40094258

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 2)

Name: PWM_DTUPD2

Access: write-only

Address: 0x4009425C

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 3)

Name: PWM_CMR3

Access: read-write

Address: 0x40094260

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 3)

Name: PWM_CDTY3

Access: read-write

Address: 0x40094264

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 3)

Name: PWM_CDTYUPD3

Access: write-only

Address: 0x40094268

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 3)

Name: PWM_CPRD3

Access: read-write

Address: 0x4009426C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 3)

Name: PWM_CPRDUPD3

Access: write-only

Address: 0x40094270

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 3)

Name: PWM_CCNT3

Access: read-only

Address: 0x40094274

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 3)

Name: PWM_DT3

Access: read-write

Address: 0x40094278

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 3)

Name: PWM_DTUPD3

Access: write-only

Address: 0x4009427C

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 4)

Name: PWM_CMR4

Access: read-write

Address: 0x40094280

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 4)

Name: PWM_CDTY4

Access: read-write

Address: 0x40094284

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 4)

Name: PWM_CDTYUPD4

Access: write-only

Address: 0x40094288

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 4)

Name: PWM_CPRD4

Access: read-write

Address: 0x4009428C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 4)

Name: PWM_CPRDUPD4

Access: write-only

Address: 0x40094290

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 4)

Name: PWM_CCNT4

Access: read-only

Address: 0x40094294

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 4)

Name: PWM_DT4

Access: read-write

Address: 0x40094298

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 4)

Name: PWM_DTUPD4

Access: write-only

Address: 0x4009429C

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 5)

Name: PWM_CMR5

Access: read-write

Address: 0x400942A0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 5)

Name: PWM_CDTY5

Access: read-write

Address: 0x400942A4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 5)

Name: PWM_CDTYUPD5

Access: write-only

Address: 0x400942A8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 5)

Name: PWM_CPRD5

Access: read-write

Address: 0x400942AC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 5)

Name: PWM_CPRDUPD5

Access: write-only

Address: 0x400942B0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 5)

Name: PWM_CCNT5

Access: read-only

Address: 0x400942B4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 5)

Name: PWM_DT5

Access: read-write

Address: 0x400942B8

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 5)

Name: PWM_DTUPD5

Access: write-only

Address: 0x400942BC

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 6)

Name: PWM_CMR6

Access: read-write

Address: 0x400942C0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 6)

Name: PWM_CDTY6

Access: read-write

Address: 0x400942C4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 6)

Name: PWM_CDTYUPD6

Access: write-only

Address: 0x400942C8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 6)

Name: PWM_CPRD6

Access: read-write

Address: 0x400942CC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 6)

Name: PWM_CPRDUPD6

Access: write-only

Address: 0x400942D0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 6)

Name: PWM_CCNT6

Access: read-only

Address: 0x400942D4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 6)

Name: PWM_DT6

Access: read-write

Address: 0x400942D8

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 6)

Name: PWM_DTUPD6

Access: write-only

Address: 0x400942DC

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM PWM Channel Mode Register (ch_num = 7)

Name: PWM_CMR7

Access: read-write

Address: 0x400942E0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	DTLI	DTHI	DTE
15	14	13	12	11	10	9	8
-	-	-	-	-	CES	CPOL	CALG
7	6	5	4	3	2	1	0
-	-	-	-	CPRE

• CPRE: Channel Pre-scaler

  Value	Name	Description
  0x0	MCK	Master clock
  0x1	MCK_DIV_2	Master clock/2
  0x2	MCK_DIV_4	Master clock/4
  0x3	MCK_DIV_8	Master clock/8
  0x4	MCK_DIV_16	Master clock/16
  0x5	MCK_DIV_32	Master clock/32
  0x6	MCK_DIV_64	Master clock/64
  0x7	MCK_DIV_128	Master clock/128
  0x8	MCK_DIV_256	Master clock/256
  0x9	MCK_DIV_512	Master clock/512
  0xA	MCK_DIV_1024	Master clock/1024
  0xB	CLKA	Clock A
  0xC	CLKB	Clock B

• CALG: Channel Alignment

  Value	Name	Description
  0	-	The period is left aligned.
  1	-	The period is center aligned.

• CPOL: Channel Polarity

  Value	Name	Description
  0	-	The OCx output waveform (output from the comparator) starts at a low level.
  1	-	The OCx output waveform (output from the comparator) starts at a high level.

• CES: Counter Event Selection

  Value	Name	Description
  0	-	The channel counter event occurs at the end of the PWM period.
  1	-	The channel counter event occurs at the end of the PWM period and at half the PWM period.

• DTE: Dead-Time Generator Enable

  Value	Name	Description
  0	-	The dead-time generator is disabled.
  1	-	The dead-time generator is enabled.

• DTHI: Dead-Time PWMHx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMHx output is not inverted.
  1	-	The dead-time PWMHx output is inverted.

• DTLI: Dead-Time PWMLx Output Inverted

  Value	Name	Description
  0	-	The dead-time PWMLx output is not inverted.
  1	-	The dead-time PWMLx output is inverted.

PWM PWM Channel Duty Cycle Register (ch_num = 7)

Name: PWM_CDTY7

Access: read-write

Address: 0x400942E4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTY
15	14	13	12	11	10	9	8
CDTY
7	6	5	4	3	2	1	0
CDTY

• CDTY: Channel Duty-Cycle

-

PWM PWM Channel Duty Cycle Update Register (ch_num = 7)

Name: PWM_CDTYUPD7

Access: write-only

Address: 0x400942E8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CDTYUPD
15	14	13	12	11	10	9	8
CDTYUPD
7	6	5	4	3	2	1	0
CDTYUPD

• CDTYUPD: Channel Duty-Cycle Update

-

PWM PWM Channel Period Register (ch_num = 7)

Name: PWM_CPRD7

Access: read-write

Address: 0x400942EC

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRD
15	14	13	12	11	10	9	8
CPRD
7	6	5	4	3	2	1	0
CPRD

• CPRD: Channel Period

-

PWM PWM Channel Period Update Register (ch_num = 7)

Name: PWM_CPRDUPD7

Access: write-only

Address: 0x400942F0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CPRDUPD
15	14	13	12	11	10	9	8
CPRDUPD
7	6	5	4	3	2	1	0
CPRDUPD

• CPRDUPD: Channel Period Update

-

PWM PWM Channel Counter Register (ch_num = 7)

Name: PWM_CCNT7

Access: read-only

Address: 0x400942F4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
CNT
15	14	13	12	11	10	9	8
CNT
7	6	5	4	3	2	1	0
CNT

• CNT: Channel Counter Register

-

PWM PWM Channel Dead Time Register (ch_num = 7)

Name: PWM_DT7

Access: read-write

Address: 0x400942F8

31	30	29	28	27	26	25	24
DTL
23	22	21	20	19	18	17	16
DTL
15	14	13	12	11	10	9	8
DTH
7	6	5	4	3	2	1	0
DTH

• DTH: Dead-Time Value for PWMHx Output

-

• DTL: Dead-Time Value for PWMLx Output

-

PWM PWM Channel Dead Time Update Register (ch_num = 7)

Name: PWM_DTUPD7

Access: write-only

Address: 0x400942FC

31	30	29	28	27	26	25	24
DTLUPD
23	22	21	20	19	18	17	16
DTLUPD
15	14	13	12	11	10	9	8
DTHUPD
7	6	5	4	3	2	1	0
DTHUPD

• DTHUPD: Dead-Time Value Update for PWMHx Output

-

• DTLUPD: Dead-Time Value Update for PWMLx Output

-

PWM Transmit Pointer Register

Name: PWM_TPR

Access: read-write

Address: 0x40094108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

• TXPTR: Transmit Counter Register

-

PWM Transmit Counter Register

Name: PWM_TCR

Access: read-write

Address: 0x4009410C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

• TXCTR: Transmit Counter Register

-

PWM Transmit Next Pointer Register

Name: PWM_TNPR

Access: read-write

Address: 0x40094118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

• TXNPTR: Transmit Next Pointer

-

PWM Transmit Next Counter Register

Name: PWM_TNCR

Access: read-write

Address: 0x4009411C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCTR
7	6	5	4	3	2	1	0
TXNCTR

• TXNCTR: Transmit Counter Next

-

PWM Transfer Control Register

Name: PWM_PTCR

Access: write-only

Address: 0x40094120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables PDC receiver channel requests if RXTDIS is not set.

• RXTDIS: Receiver Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC receiver channel requests.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the PDC transmitter channel requests.

• TXTDIS: Transmitter Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC transmitter channel requests.

PWM Transfer Status Register

Name: PWM_PTSR

Access: read-only

Address: 0x40094124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	PDC Receiver channel requests are disabled.
  1	-	PDC Receiver channel requests are enabled.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	PDC Transmitter channel requests are disabled.
  1	-	PDC Transmitter channel requests are enabled.