SAM3XA DACC

Digital-to-Analog Converter Controller (DACC) User Interface

Registers

Register Mapping

Address	Register	Name	Access	Reset
0x400C8000	Control Register	DACC_CR	write-only	-
0x400C8004	Mode Register	DACC_MR	read-write	0x00000000
0x400C8010	Channel Enable Register	DACC_CHER	write-only	-
0x400C8014	Channel Disable Register	DACC_CHDR	write-only	-
0x400C8018	Channel Status Register	DACC_CHSR	read-only	0x00000000
0x400C8020	Conversion Data Register	DACC_CDR	write-only	0x00000000
0x400C8024	Interrupt Enable Register	DACC_IER	write-only	-
0x400C8028	Interrupt Disable Register	DACC_IDR	write-only	-
0x400C802C	Interrupt Mask Register	DACC_IMR	read-only	0x00000000
0x400C8030	Interrupt Status Register	DACC_ISR	read-only	0x00000000
0x400C8094	Analog Current Register	DACC_ACR	read-write	0x00000000
0x400C80E4	Write Protect Mode register	DACC_WPMR	read-write	0x00000000
0x400C80E8	Write Protect Status register	DACC_WPSR	read-only	0x00000000
0x400C8108	Transmit Pointer Register	DACC_TPR	read-write	0x00000000
0x400C810C	Transmit Counter Register	DACC_TCR	read-write	0x00000000
0x400C8118	Transmit Next Pointer Register	DACC_TNPR	read-write	0x00000000
0x400C811C	Transmit Next Counter Register	DACC_TNCR	read-write	0x00000000
0x400C8120	Transfer Control Register	DACC_PTCR	write-only	0x00000000
0x400C8124	Transfer Status Register	DACC_PTSR	read-only	0x00000000

Register Fields

DACC Control Register

Name: DACC_CR

Access: write-only

Address: 0x400C8000

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	SWRST

• SWRST: Software Reset

  Value	Name	Description
  0	-	No effect.
  1	-	Resets the DACC simulating a hardware reset.

DACC Mode Register

Name: DACC_MR

Access: read-write

Address: 0x400C8004

31	30	29	28	27	26	25	24
-	-	STARTUP
23	22	21	20	19	18	17	16
-	-	MAXS	TAG	-	-	USER_SEL
15	14	13	12	11	10	9	8
REFRESH
7	6	5	4	3	2	1	0
-	FASTWKUP	SLEEP	WORD	TRGSEL			TRGEN

• TRGEN: Trigger Enable

  Value	Name	Description
  0	DIS	External trigger mode disabled. DACC in free running mode.
  1	EN	External trigger mode enabled.

• TRGSEL: Trigger Selection

  Value	Name	Description
  0x0	-	External trigger
  0x1	-	TIO Output of the Timer Counter Channel 0
  0x2	-	TIO Output of the Timer Counter Channel 1
  0x3	-	TIO Output of the Timer Counter Channel 2
  0x4	-	PWM Event Line 0
  0x5	-	PWM Event Line 1

• WORD: Word Transfer

  Value	Name	Description
  0	HALF	Half-Word transfer
  1	WORD	Word Transfer

• SLEEP: Sleep Mode

-

• FASTWKUP: Fast Wake up Mode

  Value	Name	Description
  0x0	-	Normal Sleep Mode
  0x1	-	Fast Wake up Sleep Mode

• REFRESH: Refresh Period

-

• USER_SEL: User Channel Selection

  Value	Name	Description
  0	CHANNEL0	Channel 0
  1	CHANNEL1	Channel 1

• TAG: Tag Selection Mode

  Value	Name	Description
  0	DIS	Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
  1	EN	Tag selection mode enabled

• MAXS: Max Speed Mode

  Value	Name	Description
  0	NORMAL	Normal Mode
  1	MAXIMUM	Max Speed Mode enabled

• STARTUP: Startup Time Selection

  Value	Name	Description
  0x0	0	0 periods of DACClock
  0x1	8	8 periods of DACClock
  0x2	16	16 periods of DACClock
  0x3	24	24 periods of DACClock
  0x4	64	64 periods of DACClock
  0x5	80	80 periods of DACClock
  0x6	96	96 periods of DACClock
  0x7	112	112 periods of DACClock
  0x8	512	512 periods of DACClock
  0x9	576	576 periods of DACClock
  0xA	640	640 periods of DACClock
  0xB	704	704 periods of DACClock
  0xC	768	768 periods of DACClock
  0xD	832	832 periods of DACClock
  0xE	896	896 periods of DACClock
  0xF	960	960 periods of DACClock
  0x10	1024	1024 periods of DACClock
  0x11	1088	1088 periods of DACClock
  0x12	1152	1152 periods of DACClock
  0x13	1216	1216 periods of DACClock
  0x14	1280	1280 periods of DACClock
  0x15	1344	1344 periods of DACClock
  0x16	1408	1408 periods of DACClock
  0x17	1472	1472 periods of DACClock
  0x18	1536	1536 periods of DACClock
  0x19	1600	1600 periods of DACClock
  0x1A	1664	1664 periods of DACClock
  0x1B	1728	1728 periods of DACClock
  0x1C	1792	1792 periods of DACClock
  0x1D	1856	1856 periods of DACClock
  0x1E	1920	1920 periods of DACClock
  0x1F	1984	1984 periods of DACClock

DACC Channel Enable Register

Name: DACC_CHER

Access: write-only

Address: 0x400C8010

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	CH1	CH0

• CH0: Channel 0 Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the corresponding channel.

• CH1: Channel 1 Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the corresponding channel.

DACC Channel Disable Register

Name: DACC_CHDR

Access: write-only

Address: 0x400C8014

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	CH1	CH0

• CH0: Channel 0 Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the corresponding channel.

• CH1: Channel 1 Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the corresponding channel.

DACC Channel Status Register

Name: DACC_CHSR

Access: read-only

Address: 0x400C8018

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	-	-	CH1	CH0

• CH0: Channel 0 Status

  Value	Name	Description
  0	-	Corresponding channel is disabled.
  1	-	Corresponding channel is enabled.

• CH1: Channel 1 Status

  Value	Name	Description
  0	-	Corresponding channel is disabled.
  1	-	Corresponding channel is enabled.

DACC Conversion Data Register

Name: DACC_CDR

Access: write-only

Address: 0x400C8020

31	30	29	28	27	26	25	24
DATA
23	22	21	20	19	18	17	16
DATA
15	14	13	12	11	10	9	8
DATA
7	6	5	4	3	2	1	0
DATA

• DATA: Data to Convert

-

DACC Interrupt Enable Register

Name: DACC_IER

Access: write-only

Address: 0x400C8024

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	TXBUFE	ENDTX	EOC	TXRDY

• TXRDY: Transmit Ready Interrupt Enable

-

• EOC: End of Conversion Interrupt Enable

-

• ENDTX: End of Transmit Buffer Interrupt Enable

-

• TXBUFE: Transmit Buffer Empty Interrupt Enable

-

DACC Interrupt Disable Register

Name: DACC_IDR

Access: write-only

Address: 0x400C8028

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	TXBUFE	ENDTX	EOC	TXRDY

• TXRDY: Transmit Ready Interrupt Disable.

-

• EOC: End of Conversion Interrupt Disable

-

• ENDTX: End of Transmit Buffer Interrupt Disable

-

• TXBUFE: Transmit Buffer Empty Interrupt Disable

-

DACC Interrupt Mask Register

Name: DACC_IMR

Access: read-only

Address: 0x400C802C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	TXBUFE	ENDTX	EOC	TXRDY

• TXRDY: Transmit Ready Interrupt Mask

-

• EOC: End of Conversion Interrupt Mask

-

• ENDTX: End of Transmit Buffer Interrupt Mask

-

• TXBUFE: Transmit Buffer Empty Interrupt Mask

-

DACC Interrupt Status Register

Name: DACC_ISR

Access: read-only

Address: 0x400C8030

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-
7	6	5	4	3	2	1	0
-	-	-	-	TXBUFE	ENDTX	EOC	TXRDY

• TXRDY: Transmit Ready Interrupt Flag

  Value	Name	Description
  0	-	DACC is not ready to accept new conversion requests.
  1	-	DACC is ready to accept new conversion requests.

• EOC: End of Conversion Interrupt Flag

  Value	Name	Description
  0	-	no conversion has been performed since the last DACC_ISR read.
  1	-	at least one conversion has been performed since the last DACC_ISR read.

• ENDTX: End of DMA Interrupt Flag

  Value	Name	Description
  0	-	the Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
  1	-	the Transmit Counter Register has reached 0 since the last write in DACC _TCR or DACC_TNCR

• TXBUFE: Transmit Buffer Empty

  Value	Name	Description
  0	-	the Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
  1	-	the Transmit Counter Register has reached 0 since the last write in DACC _TCR or DACC_TNCR.

DACC Analog Current Register

Name: DACC_ACR

Access: read-write

Address: 0x400C8094

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	IBCTLDACCORE
7	6	5	4	3	2	1	0
-	-	-	-	IBCTLCH1		IBCTLCH0

• IBCTLCH0: Analog Output Current Control

-

• IBCTLCH1: Analog Output Current Control

-

• IBCTLDACCORE: Bias Current Control for DAC Core

-

DACC Write Protect Mode register

Name: DACC_WPMR

Access: read-write

Address: 0x400C80E4

31	30	29	28	27	26	25	24
WPKEY
23	22	21	20	19	18	17	16
WPKEY
15	14	13	12	11	10	9	8
WPKEY
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	WPEN

• WPEN: Write Protect Enable

  Value	Name	Description
  0	-	Disables the Write Protect if WPKEY corresponds to 0x444143 ("DAC" in ASCII).
  1	-	Enables the Write Protect if WPKEY corresponds to 0x444143 ("DAC" in ASCII).

• WPKEY: Write Protect KEY

-

DACC Write Protect Status register

Name: DACC_WPSR

Access: read-only

Address: 0x400C80E8

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
WPROTADDR
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	WPROTERR

• WPROTERR: Write protection error

-

• WPROTADDR: Write protection error address

-

DACC Transmit Pointer Register

Name: DACC_TPR

Access: read-write

Address: 0x400C8108

31	30	29	28	27	26	25	24
TXPTR
23	22	21	20	19	18	17	16
TXPTR
15	14	13	12	11	10	9	8
TXPTR
7	6	5	4	3	2	1	0
TXPTR

• TXPTR: Transmit Counter Register

-

DACC Transmit Counter Register

Name: DACC_TCR

Access: read-write

Address: 0x400C810C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXCTR
7	6	5	4	3	2	1	0
TXCTR

• TXCTR: Transmit Counter Register

-

DACC Transmit Next Pointer Register

Name: DACC_TNPR

Access: read-write

Address: 0x400C8118

31	30	29	28	27	26	25	24
TXNPTR
23	22	21	20	19	18	17	16
TXNPTR
15	14	13	12	11	10	9	8
TXNPTR
7	6	5	4	3	2	1	0
TXNPTR

• TXNPTR: Transmit Next Pointer

-

DACC Transmit Next Counter Register

Name: DACC_TNCR

Access: read-write

Address: 0x400C811C

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
TXNCTR
7	6	5	4	3	2	1	0
TXNCTR

• TXNCTR: Transmit Counter Next

-

DACC Transfer Control Register

Name: DACC_PTCR

Access: write-only

Address: 0x400C8120

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	TXTDIS	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	RXTDIS	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables PDC receiver channel requests if RXTDIS is not set.

• RXTDIS: Receiver Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC receiver channel requests.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	No effect.
  1	-	Enables the PDC transmitter channel requests.

• TXTDIS: Transmitter Transfer Disable

  Value	Name	Description
  0	-	No effect.
  1	-	Disables the PDC transmitter channel requests.

DACC Transfer Status Register

Name: DACC_PTSR

Access: read-only

Address: 0x400C8124

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-
23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-
15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	TXTEN
7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RXTEN

• RXTEN: Receiver Transfer Enable

  Value	Name	Description
  0	-	PDC Receiver channel requests are disabled.
  1	-	PDC Receiver channel requests are enabled.

• TXTEN: Transmitter Transfer Enable

  Value	Name	Description
  0	-	PDC Transmitter channel requests are disabled.
  1	-	PDC Transmitter channel requests are enabled.