SAM3XA SSC
Synchronous Serial Controller (SSC) User Interface
Registers
Address | Register | Name | Access | Reset |
---|---|---|---|---|
0x40004000 | Control Register | SSC_CR | write-only | - |
0x40004004 | Clock Mode Register | SSC_CMR | read-write | 0x00000000 |
0x40004010 | Receive Clock Mode Register | SSC_RCMR | read-write | 0x00000000 |
0x40004014 | Receive Frame Mode Register | SSC_RFMR | read-write | 0x00000000 |
0x40004018 | Transmit Clock Mode Register | SSC_TCMR | read-write | 0x00000000 |
0x4000401C | Transmit Frame Mode Register | SSC_TFMR | read-write | 0x00000000 |
0x40004020 | Receive Holding Register | SSC_RHR | read-only | 0x00000000 |
0x40004024 | Transmit Holding Register | SSC_THR | write-only | - |
0x40004030 | Receive Sync. Holding Register | SSC_RSHR | read-only | 0x00000000 |
0x40004034 | Transmit Sync. Holding Register | SSC_TSHR | read-write | 0x00000000 |
0x40004038 | Receive Compare 0 Register | SSC_RC0R | read-write | 0x00000000 |
0x4000403C | Receive Compare 1 Register | SSC_RC1R | read-write | 0x00000000 |
0x40004040 | Status Register | SSC_SR | read-only | 0x000000CC |
0x40004044 | Interrupt Enable Register | SSC_IER | write-only | - |
0x40004048 | Interrupt Disable Register | SSC_IDR | write-only | - |
0x4000404C | Interrupt Mask Register | SSC_IMR | read-only | 0x00000000 |
0x400040E4 | Write Protect Mode Register | SSC_WPMR | read-write | 0x00000000 |
0x400040E8 | Write Protect Status Register | SSC_WPSR | read-only | 0x00000000 |
Register Fields
SSC Control Register
Name: SSC_CR
Access: write-only
Address: 0x40004000
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SWRST | - | - | - | - | - | TXDIS | TXEN |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | RXDIS | RXEN |
- RXEN: Receive Enable
Value Name Description 0 - No effect. 1 - Enables Receive if RXDIS is not set. - RXDIS: Receive Disable
Value Name Description 0 - No effect. 1 - Disables Receive. If a character is currently being received, disables at end of current character reception. - TXEN: Transmit Enable
Value Name Description 0 - No effect. 1 - Enables Transmit if TXDIS is not set. - TXDIS: Transmit Disable
Value Name Description 0 - No effect. 1 - Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. - SWRST: Software Reset
Value Name Description 0 - No effect. 1 - Performs a software reset. Has priority on any other bit in SSC_CR.
SSC Clock Mode Register
Name: SSC_CMR
Access: read-write
Address: 0x40004004
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DIV | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV |
- DIV: Clock Divider
Value Name Description 0 - The Clock Divider is not active.
SSC Receive Clock Mode Register
Name: SSC_RCMR
Access: read-write
Address: 0x40004010
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PERIOD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STTDLY | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | STOP | START | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKG | CKI | CKO | CKS |
- CKS: Receive Clock Selection
Value Name Description 0x0 MCK Divided Clock 0x1 TK TK Clock signal 0x2 RK RK pin - CKO: Receive Clock Output Mode Selection
Value Name Description 0x0 NONE None 0x1 CONTINUOUS Continuous Receive Clock 0x2 TRANSFER Receive Clock only during data transfers - CKI: Receive Clock Inversion
Value Name Description 0 - The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 - The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-put is shifted out on Receive Clock falling edge. - CKG: Receive Clock Gating Selection
Value Name Description 0x0 NONE None 0x1 CONTINUOUS Continuous Receive Clock 0x2 TRANSFER Receive Clock only during data transfers - START: Receive Start Selection
Value Name Description 0x0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 TRANSMIT Transmit start 0x2 RF_LOW Detection of a low level on RF signal 0x3 RF_HIGH Detection of a high level on RF signal 0x4 RF_FALLING Detection of a falling edge on RF signal 0x5 RF_RISING Detection of a rising edge on RF signal 0x6 RF_LEVEL Detection of any level change on RF signal 0x7 RF_EDGE Detection of any edge on RF signal 0x8 CMP_0 Compare 0 - STOP: Receive Stop Selection
Value Name Description 0 - After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 - After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. - STTDLY: Receive Start Delay
- PERIOD: Receive Period Divider Selection
-
-
SSC Receive Frame Mode Register
Name: SSC_RFMR
Access: read-write
Address: 0x40004014
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FSLEN_EXT | - | - | - | FSEDGE | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | FSOS | FSLEN | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DATNB | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSBF | - | LOOP | DATLEN |
- DATLEN: Data Length
Value Name Description 0 - Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. - LOOP: Loop Mode
Value Name Description 0 - Normal operating mode. 1 - RD is driven by TD, RF is driven by TF and TK drives RK. - MSBF: Most Significant Bit First
Value Name Description 0 - The lowest significant bit of the data register is sampled first in the bit stream. 1 - The most significant bit of the data register is sampled first in the bit stream. - DATNB: Data Number per Frame
- FSLEN: Receive Frame Sync Length
- FSOS: Receive Frame Sync Output Selection
Value Name Description 0x0 NONE None 0x1 NEGATIVE Negative Pulse 0x2 POSITIVE Positive Pulse 0x3 LOW Driven Low during data transfer 0x4 HIGH Driven High during data transfer 0x5 TOGGLING Toggling at each start of data transfer - FSEDGE: Frame Sync Edge Detection
Value Name Description 0 POSITIVE Positive Edge Detection 1 NEGATIVE Negative Edge Detection - FSLEN_EXT: FSLEN Field Extension
-
-
-
SSC Transmit Clock Mode Register
Name: SSC_TCMR
Access: read-write
Address: 0x40004018
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PERIOD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STTDLY | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | START | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKG | CKI | CKO | CKS |
- CKS: Transmit Clock Selection
Value Name Description 0x0 MCK Divided Clock 0x1 TK TK Clock signal 0x2 RK RK pin - CKO: Transmit Clock Output Mode Selection
Value Name Description 0x0 NONE None 0x1 CONTINUOUS Continuous Receive Clock 0x2 TRANSFER Transmit Clock only during data transfers - CKI: Transmit Clock Inversion
Value Name Description 0 - The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 - The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. - CKG: Transmit Clock Gating Selection
Value Name Description 0x0 NONE None 0x1 CONTINUOUS Transmit Clock enabled only if TF Low 0x2 TRANSFER Transmit Clock enabled only if TF High - START: Transmit Start Selection
Value Name Description 0x0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 RECEIVE Receive start 0x2 RF_LOW Detection of a low level on TF signal 0x3 RF_HIGH Detection of a high level on TF signal 0x4 RF_FALLING Detection of a falling edge on TF signal 0x5 RF_RISING Detection of a rising edge on TF signal 0x6 RF_LEVEL Detection of any level change on TF signal 0x7 RF_EDGE Detection of any edge on TF signal 0x8 CMP_0 Compare 0 - STTDLY: Transmit Start Delay
- PERIOD: Transmit Period Divider Selection
-
-
SSC Transmit Frame Mode Register
Name: SSC_TFMR
Access: read-write
Address: 0x4000401C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FSLEN_EXT | - | - | - | FSEDGE | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FSDEN | FSOS | FSLEN | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DATNB | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSBF | - | DATDEF | DATLEN |
- DATLEN: Data Length
Value Name Description 0 - Forbidden value (1-bit data length not supported). - DATDEF: Data Default Value
- MSBF: Most Significant Bit First
Value Name Description 0 - The lowest significant bit of the data register is shifted out first in the bit stream. 1 - The most significant bit of the data register is shifted out first in the bit stream. - DATNB: Data Number per frame
- FSLEN: Transmit Frame Sync Length
- FSOS: Transmit Frame Sync Output Selection
Value Name Description 0x0 NONE None 0x1 NEGATIVE Negative Pulse 0x2 POSITIVE Positive Pulse 0x3 LOW Driven Low during data transfer 0x4 HIGH Driven High during data transfer 0x5 TOGGLING Toggling at each start of data transfer - FSDEN: Frame Sync Data Enable
Value Name Description 0 - The TD line is driven with the default value during the Transmit Frame Sync signal. 1 - SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. - FSEDGE: Frame Sync Edge Detection
Value Name Description 0 POSITIVE Positive Edge Detection 1 NEGATIVE Negative Edge Detection - FSLEN_EXT: FSLEN Field Extension
-
-
-
-
SSC Receive Holding Register
Name: SSC_RHR
Access: read-only
Address: 0x40004020
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RDAT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RDAT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RDAT | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDAT |
- RDAT: Receive Data
-
SSC Transmit Holding Register
Name: SSC_THR
Access: write-only
Address: 0x40004024
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TDAT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TDAT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TDAT | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDAT |
- TDAT: Transmit Data
-
SSC Receive Sync. Holding Register
Name: SSC_RSHR
Access: read-only
Address: 0x40004030
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RSDAT | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSDAT |
- RSDAT: Receive Synchronization Data
-
SSC Transmit Sync. Holding Register
Name: SSC_TSHR
Access: read-write
Address: 0x40004034
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TSDAT | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSDAT |
- TSDAT: Transmit Synchronization Data
-
SSC Receive Compare 0 Register
Name: SSC_RC0R
Access: read-write
Address: 0x40004038
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CP0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CP0 |
- CP0: Receive Compare Data 0
-
SSC Receive Compare 1 Register
Name: SSC_RC1R
Access: read-write
Address: 0x4000403C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CP1 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CP1 |
- CP1: Receive Compare Data 1
-
SSC Status Register
Name: SSC_SR
Access: read-only
Address: 0x40004040
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | RXEN | TXEN |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | RXSYN | TXSYN | CP1 | CP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | OVRUN | RXRDY | - | - | TXEMPTY | TXRDY |
- TXRDY: Transmit Ready
Value Name Description 0 - Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 - SSC_THR is empty. - TXEMPTY: Transmit Empty
Value Name Description 0 - Data remains in SSC_THR or is currently transmitted from TSR. 1 - Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. - RXRDY: Receive Ready
Value Name Description 0 - SSC_RHR is empty. 1 - Data has been received and loaded in SSC_RHR. - OVRUN: Receive Overrun
Value Name Description 0 - No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 - Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. - CP0: Compare 0
Value Name Description 0 - A compare 0 has not occurred since the last read of the Status Register. 1 - A compare 0 has occurred since the last read of the Status Register. - CP1: Compare 1
Value Name Description 0 - A compare 1 has not occurred since the last read of the Status Register. 1 - A compare 1 has occurred since the last read of the Status Register. - TXSYN: Transmit Sync
Value Name Description 0 - A Tx Sync has not occurred since the last read of the Status Register. 1 - A Tx Sync has occurred since the last read of the Status Register. - RXSYN: Receive Sync
Value Name Description 0 - An Rx Sync has not occurred since the last read of the Status Register. 1 - An Rx Sync has occurred since the last read of the Status Register. - TXEN: Transmit Enable
Value Name Description 0 - Transmit is disabled. 1 - Transmit is enabled. - RXEN: Receive Enable
Value Name Description 0 - Receive is disabled. 1 - Receive is enabled.
SSC Interrupt Enable Register
Name: SSC_IER
Access: write-only
Address: 0x40004044
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | RXSYN | TXSYN | CP1 | CP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | OVRUN | RXRDY | - | - | TXEMPTY | TXRDY |
- TXRDY: Transmit Ready Interrupt Enable
Value Name Description 0 - 0 = No effect. 1 - Enables the Transmit Ready Interrupt. - TXEMPTY: Transmit Empty Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Transmit Empty Interrupt. - RXRDY: Receive Ready Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Receive Ready Interrupt. - OVRUN: Receive Overrun Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Receive Overrun Interrupt. - CP0: Compare 0 Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Compare 0 Interrupt. - CP1: Compare 1 Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Compare 1 Interrupt. - TXSYN: Tx Sync Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Tx Sync Interrupt. - RXSYN: Rx Sync Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the Rx Sync Interrupt.
SSC Interrupt Disable Register
Name: SSC_IDR
Access: write-only
Address: 0x40004048
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | RXSYN | TXSYN | CP1 | CP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | OVRUN | RXRDY | - | - | TXEMPTY | TXRDY |
- TXRDY: Transmit Ready Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Transmit Ready Interrupt. - TXEMPTY: Transmit Empty Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Transmit Empty Interrupt. - RXRDY: Receive Ready Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Receive Ready Interrupt. - OVRUN: Receive Overrun Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Receive Overrun Interrupt. - CP0: Compare 0 Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Compare 0 Interrupt. - CP1: Compare 1 Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the Compare 1 Interrupt. - TXSYN: Tx Sync Interrupt Enable
Value Name Description 0 - No effect. 1 - Disables the Tx Sync Interrupt. - RXSYN: Rx Sync Interrupt Enable
Value Name Description 0 - No effect. 1 - Disables the Rx Sync Interrupt.
SSC Interrupt Mask Register
Name: SSC_IMR
Access: read-only
Address: 0x4000404C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | RXSYN | TXSYN | CP1 | CP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | OVRUN | RXRDY | - | - | TXEMPTY | TXRDY |
- TXRDY: Transmit Ready Interrupt Mask
Value Name Description 0 - The Transmit Ready Interrupt is disabled. 1 - The Transmit Ready Interrupt is enabled. - TXEMPTY: Transmit Empty Interrupt Mask
Value Name Description 0 - The Transmit Empty Interrupt is disabled. 1 - The Transmit Empty Interrupt is enabled. - RXRDY: Receive Ready Interrupt Mask
Value Name Description 0 - The Receive Ready Interrupt is disabled. 1 - The Receive Ready Interrupt is enabled. - OVRUN: Receive Overrun Interrupt Mask
Value Name Description 0 - The Receive Overrun Interrupt is disabled. 1 - The Receive Overrun Interrupt is enabled. - CP0: Compare 0 Interrupt Mask
Value Name Description 0 - The Compare 0 Interrupt is disabled. 1 - The Compare 0 Interrupt is enabled. - CP1: Compare 1 Interrupt Mask
Value Name Description 0 - The Compare 1 Interrupt is disabled. 1 - The Compare 1 Interrupt is enabled. - TXSYN: Tx Sync Interrupt Mask
Value Name Description 0 - The Tx Sync Interrupt is disabled. 1 - The Tx Sync Interrupt is enabled. - RXSYN: Rx Sync Interrupt Mask
Value Name Description 0 - The Rx Sync Interrupt is disabled. 1 - The Rx Sync Interrupt is enabled.
SSC Write Protect Mode Register
Name: SSC_WPMR
Access: read-write
Address: 0x400040E4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WPKEY | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPKEY | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPKEY | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPEN |
- WPEN: Write Protect Enable
Value Name Description 0 - Disables the Write Protect if WPKEY corresponds to 0x535343 ("SSC" in ASCII). 1 - Enables the Write Protect if WPKEY corresponds to 0x535343 ("SSC" in ASCII). - WPKEY: Write Protect KEY
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SSC Write Protect Status Register
Name: SSC_WPSR
Access: read-only
Address: 0x400040E8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPVSRC | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPVSRC | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPVS |
- WPVS: Write Protect Violation Status
Value Name Description 0 - No Write Protect Violation has occurred since the last read of the SSC_WPSR register. 1 - A Write Protect Violation has occurred since the last read of the SSC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. - WPVSRC: Write Protect Violation Source
-