SAM3XA TWI0
Two-wire Interface (TWI0) User Interface
Registers
Address | Register | Name | Access | Reset |
---|---|---|---|---|
0x4008C000 | Control Register | TWI0_CR | write-only | - |
0x4008C004 | Master Mode Register | TWI0_MMR | read-write | 0x00000000 |
0x4008C008 | Slave Mode Register | TWI0_SMR | read-write | 0x00000000 |
0x4008C00C | Internal Address Register | TWI0_IADR | read-write | 0x00000000 |
0x4008C010 | Clock Waveform Generator Register | TWI0_CWGR | read-write | 0x00000000 |
0x4008C020 | Status Register | TWI0_SR | read-only | 0x0000F009 |
0x4008C024 | Interrupt Enable Register | TWI0_IER | write-only | - |
0x4008C028 | Interrupt Disable Register | TWI0_IDR | write-only | - |
0x4008C02C | Interrupt Mask Register | TWI0_IMR | read-only | 0x00000000 |
0x4008C030 | Receive Holding Register | TWI0_RHR | read-only | 0x00000000 |
0x4008C034 | Transmit Holding Register | TWI0_THR | write-only | 0x00000000 |
0x4008C100 | Receive Pointer Register | TWI0_RPR | read-write | 0x00000000 |
0x4008C104 | Receive Counter Register | TWI0_RCR | read-write | 0x00000000 |
0x4008C108 | Transmit Pointer Register | TWI0_TPR | read-write | 0x00000000 |
0x4008C10C | Transmit Counter Register | TWI0_TCR | read-write | 0x00000000 |
0x4008C110 | Receive Next Pointer Register | TWI0_RNPR | read-write | 0x00000000 |
0x4008C114 | Receive Next Counter Register | TWI0_RNCR | read-write | 0x00000000 |
0x4008C118 | Transmit Next Pointer Register | TWI0_TNPR | read-write | 0x00000000 |
0x4008C11C | Transmit Next Counter Register | TWI0_TNCR | read-write | 0x00000000 |
0x4008C120 | Transfer Control Register | TWI0_PTCR | write-only | 0x00000000 |
0x4008C124 | Transfer Status Register | TWI0_PTSR | read-only | 0x00000000 |
Register Fields
TWI0 Control Register
Name: TWI0_CR
Access: write-only
Address: 0x4008C000
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWRST | QUICK | SVDIS | SVEN | MSDIS | MSEN | STOP | START |
- START: Send a START Condition
Value Name Description 0 - No effect. 1 - A frame beginning with a START bit is transmitted according to the features defined in the mode register. - STOP: Send a STOP Condition
Value Name Description 0 - No effect. 1 - STOP Condition is sent just after completing the current byte transmission in master read mode. - MSEN: TWI Master Mode Enabled
Value Name Description 0 - No effect. 1 - If MSDIS = 0, the master mode is enabled. - MSDIS: TWI Master Mode Disabled
Value Name Description 0 - No effect. 1 - The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. - SVEN: TWI Slave Mode Enabled
Value Name Description 0 - No effect. 1 - If SVDIS = 0, the slave mode is enabled. - SVDIS: TWI Slave Mode Disabled
Value Name Description 0 - No effect. 1 - The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read oper-ation. In write operation, the character being transferred must be completely received before disabling. - QUICK: SMBUS Quick Command
Value Name Description 0 - No effect. 1 - If Master mode is enabled, a SMBUS Quick Command is sent. - SWRST: Software Reset
Value Name Description 0 - No effect. 1 - Equivalent to a system reset.
TWI0 Master Mode Register
Name: TWI0_MMR
Access: read-write
Address: 0x4008C004
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DADR | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | MREAD | - | - | IADRSZ | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- IADRSZ: Internal Device Address Size
Value Name Description 0x0 NONE No internal device address 0x1 1_BYTE One-byte internal device address 0x2 2_BYTE Two-byte internal device address 0x3 3_BYTE Three-byte internal device address - MREAD: Master Read Direction
Value Name Description 0 - Master write direction. 1 - Master read direction. - DADR: Device Address
-
TWI0 Slave Mode Register
Name: TWI0_SMR
Access: read-write
Address: 0x4008C008
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | SADR | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SADR: Slave Address
-
TWI0 Internal Address Register
Name: TWI0_IADR
Access: read-write
Address: 0x4008C00C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IADR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IADR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IADR |
- IADR: Internal Address
-
TWI0 Clock Waveform Generator Register
Name: TWI0_CWGR
Access: read-write
Address: 0x4008C010
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | CKDIV | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CHDIV | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLDIV |
- CLDIV: Clock Low Divider
- CHDIV: Clock High Divider
- CKDIV: Clock Divider
-
-
-
TWI0 Status Register
Name: TWI0_SR
Access: read-only
Address: 0x4008C020
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXBUFE | RXBUFF | ENDTX | ENDRX | EOSACC | SCLWS | ARBLST | NACK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | OVRE | GACC | SVACC | SVREAD | TXRDY | RXRDY | TXCOMP |
- TXCOMP: Transmission Completed (automatically set / reset)
- RXRDY: Receive Holding Register Ready (automatically set / reset)
Value Name Description 0 - No character has been received since the last TWI_RHR read operation. 1 - A byte has been received in the TWI_RHR since the last read. - TXRDY: Transmit Holding Register Ready (automatically set / reset)
- SVREAD: Slave Read (automatically set / reset)
Value Name Description 0 - Indicates that a write access is performed by a Master. 1 - Indicates that a read access is performed by a Master. - SVACC: Slave Access (automatically set / reset)
Value Name Description 0 - TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 - Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. - GACC: General Call Access (clear on read)
Value Name Description 0 - No General Call has been detected. 1 - A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. - OVRE: Overrun Error (clear on read)
Value Name Description 0 - TWI_RHR has not been loaded while RXRDY was set 1 - TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. - NACK: Not Acknowledged (clear on read)
- ARBLST: Arbitration Lost (clear on read)
Value Name Description 0 - Arbitration won. 1 - Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. - SCLWS: Clock Wait State (automatically set / reset)
Value Name Description 0 - The clock is not stretched. 1 - The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. - EOSACC: End Of Slave Access (clear on read)
Value Name Description 0 - A slave access is being performing. 1 - The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. - ENDRX: End of RX buffer
Value Name Description 0 - The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1 - The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. - ENDTX: End of TX buffer
Value Name Description 0 - The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1 - The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. - RXBUFF: RX Buffer Full
Value Name Description 0 - TWI_RCR or TWI_RNCR have a value other than 0. 1 - Both TWI_RCR and TWI_RNCR have a value of 0. - TXBUFE: TX Buffer Empty
Value Name Description 0 - TWI_TCR or TWI_TNCR have a value other than 0. 1 - Both TWI_TCR and TWI_TNCR have a value of 0.
-
-
-
TWI0 Interrupt Enable Register
Name: TWI0_IER
Access: write-only
Address: 0x4008C024
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXBUFE | RXBUFF | ENDTX | ENDRX | EOSACC | SCL_WS | ARBLST | NACK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | OVRE | GACC | SVACC | - | TXRDY | RXRDY | TXCOMP |
- TXCOMP: Transmission Completed Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - RXRDY: Receive Holding Register Ready Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - TXRDY: Transmit Holding Register Ready Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - SVACC: Slave Access Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - GACC: General Call Access Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - OVRE: Overrun Error Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - NACK: Not Acknowledge Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - ARBLST: Arbitration Lost Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - SCL_WS: Clock Wait State Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - EOSACC: End Of Slave Access Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - ENDRX: End of Receive Buffer Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - ENDTX: End of Transmit Buffer Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - RXBUFF: Receive Buffer Full Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt. - TXBUFE: Transmit Buffer Empty Interrupt Enable
Value Name Description 0 - No effect. 1 - Enables the corresponding interrupt.
TWI0 Interrupt Disable Register
Name: TWI0_IDR
Access: write-only
Address: 0x4008C028
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXBUFE | RXBUFF | ENDTX | ENDRX | EOSACC | SCL_WS | ARBLST | NACK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | OVRE | GACC | SVACC | - | TXRDY | RXRDY | TXCOMP |
- TXCOMP: Transmission Completed Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - RXRDY: Receive Holding Register Ready Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - TXRDY: Transmit Holding Register Ready Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - SVACC: Slave Access Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - GACC: General Call Access Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - OVRE: Overrun Error Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - NACK: Not Acknowledge Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - ARBLST: Arbitration Lost Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - SCL_WS: Clock Wait State Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - EOSACC: End Of Slave Access Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - ENDRX: End of Receive Buffer Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - ENDTX: End of Transmit Buffer Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - RXBUFF: Receive Buffer Full Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt. - TXBUFE: Transmit Buffer Empty Interrupt Disable
Value Name Description 0 - No effect. 1 - Disables the corresponding interrupt.
TWI0 Interrupt Mask Register
Name: TWI0_IMR
Access: read-only
Address: 0x4008C02C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXBUFE | RXBUFF | ENDTX | ENDRX | EOSACC | SCL_WS | ARBLST | NACK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | OVRE | GACC | SVACC | - | TXRDY | RXRDY | TXCOMP |
- TXCOMP: Transmission Completed Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - RXRDY: Receive Holding Register Ready Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - TXRDY: Transmit Holding Register Ready Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - SVACC: Slave Access Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - GACC: General Call Access Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - OVRE: Overrun Error Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - NACK: Not Acknowledge Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - ARBLST: Arbitration Lost Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - SCL_WS: Clock Wait State Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - EOSACC: End Of Slave Access Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - ENDRX: End of Receive Buffer Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - ENDTX: End of Transmit Buffer Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - RXBUFF: Receive Buffer Full Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled. - TXBUFE: Transmit Buffer Empty Interrupt Mask
Value Name Description 0 - The corresponding interrupt is disabled. 1 - The corresponding interrupt is enabled.
TWI0 Receive Holding Register
Name: TWI0_RHR
Access: read-only
Address: 0x4008C030
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA |
- RXDATA: Master or Slave Receive Holding Data
-
TWI0 Transmit Holding Register
Name: TWI0_THR
Access: write-only
Address: 0x4008C034
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA |
- TXDATA: Master or Slave Transmit Holding Data
-
TWI0 Receive Pointer Register
Name: TWI0_RPR
Access: read-write
Address: 0x4008C100
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RXPTR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RXPTR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXPTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXPTR |
- RXPTR: Receive Pointer Register
-
TWI0 Receive Counter Register
Name: TWI0_RCR
Access: read-write
Address: 0x4008C104
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXCTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXCTR |
- RXCTR: Receive Counter Register
-
TWI0 Transmit Pointer Register
Name: TWI0_TPR
Access: read-write
Address: 0x4008C108
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TXPTR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TXPTR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXPTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPTR |
- TXPTR: Transmit Counter Register
-
TWI0 Transmit Counter Register
Name: TWI0_TCR
Access: read-write
Address: 0x4008C10C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXCTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXCTR |
- TXCTR: Transmit Counter Register
-
TWI0 Receive Next Pointer Register
Name: TWI0_RNPR
Access: read-write
Address: 0x4008C110
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RXNPTR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RXNPTR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXNPTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNPTR |
- RXNPTR: Receive Next Pointer
-
TWI0 Receive Next Counter Register
Name: TWI0_RNCR
Access: read-write
Address: 0x4008C114
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXNCTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXNCTR |
- RXNCTR: Receive Next Counter
-
TWI0 Transmit Next Pointer Register
Name: TWI0_TNPR
Access: read-write
Address: 0x4008C118
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TXNPTR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TXNPTR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXNPTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXNPTR |
- TXNPTR: Transmit Next Pointer
-
TWI0 Transmit Next Counter Register
Name: TWI0_TNCR
Access: read-write
Address: 0x4008C11C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXNCTR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXNCTR |
- TXNCTR: Transmit Counter Next
-
TWI0 Transfer Control Register
Name: TWI0_PTCR
Access: write-only
Address: 0x4008C120
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | TXTDIS | TXTEN |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | RXTDIS | RXTEN |
- RXTEN: Receiver Transfer Enable
Value Name Description 0 - No effect. 1 - Enables PDC receiver channel requests if RXTDIS is not set. - RXTDIS: Receiver Transfer Disable
Value Name Description 0 - No effect. 1 - Disables the PDC receiver channel requests. - TXTEN: Transmitter Transfer Enable
Value Name Description 0 - No effect. 1 - Enables the PDC transmitter channel requests. - TXTDIS: Transmitter Transfer Disable
Value Name Description 0 - No effect. 1 - Disables the PDC transmitter channel requests.
TWI0 Transfer Status Register
Name: TWI0_PTSR
Access: read-only
Address: 0x4008C124
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | TXTEN |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | RXTEN |
- RXTEN: Receiver Transfer Enable
Value Name Description 0 - PDC Receiver channel requests are disabled. 1 - PDC Receiver channel requests are enabled. - TXTEN: Transmitter Transfer Enable
Value Name Description 0 - PDC Transmitter channel requests are disabled. 1 - PDC Transmitter channel requests are enabled.