SAM3XA DMAC
DMA Controller (DMAC) User Interface
Registers
Address | Register | Name | Access | Reset |
---|---|---|---|---|
0x400C4000 | DMAC Global Configuration Register | DMAC_GCFG | read-write | 0x00000010 |
0x400C4004 | DMAC Enable Register | DMAC_EN | read-write | 0x00000000 |
0x400C4008 | DMAC Software Single Request Register | DMAC_SREQ | read-write | 0x00000000 |
0x400C400C | DMAC Software Chunk Transfer Request Register | DMAC_CREQ | read-write | 0x00000000 |
0x400C4010 | DMAC Software Last Transfer Flag Register | DMAC_LAST | read-write | 0x00000000 |
0x400C4018 | DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. | DMAC_EBCIER | write-only | - |
0x400C401C | DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. | DMAC_EBCIDR | write-only | - |
0x400C4020 | DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. | DMAC_EBCIMR | read-only | 0x00000000 |
0x400C4024 | DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. | DMAC_EBCISR | read-only | 0x00000000 |
0x400C4028 | DMAC Channel Handler Enable Register | DMAC_CHER | write-only | - |
0x400C402C | DMAC Channel Handler Disable Register | DMAC_CHDR | write-only | - |
0x400C4030 | DMAC Channel Handler Status Register | DMAC_CHSR | read-only | 0x00FF0000 |
0x400C403C | DMAC Channel Source Address Register (ch_num = 0) | DMAC_SADDR0 | read-write | 0x00000000 |
0x400C4040 | DMAC Channel Destination Address Register (ch_num = 0) | DMAC_DADDR0 | read-write | 0x00000000 |
0x400C4044 | DMAC Channel Descriptor Address Register (ch_num = 0) | DMAC_DSCR0 | read-write | 0x00000000 |
0x400C4048 | DMAC Channel Control A Register (ch_num = 0) | DMAC_CTRLA0 | read-write | 0x00000000 |
0x400C404C | DMAC Channel Control B Register (ch_num = 0) | DMAC_CTRLB0 | read-write | 0x00000000 |
0x400C4050 | DMAC Channel Configuration Register (ch_num = 0) | DMAC_CFG0 | read-write | 0x01000000 |
0x400C4064 | DMAC Channel Source Address Register (ch_num = 1) | DMAC_SADDR1 | read-write | 0x00000000 |
0x400C4068 | DMAC Channel Destination Address Register (ch_num = 1) | DMAC_DADDR1 | read-write | 0x00000000 |
0x400C406C | DMAC Channel Descriptor Address Register (ch_num = 1) | DMAC_DSCR1 | read-write | 0x00000000 |
0x400C4070 | DMAC Channel Control A Register (ch_num = 1) | DMAC_CTRLA1 | read-write | 0x00000000 |
0x400C4074 | DMAC Channel Control B Register (ch_num = 1) | DMAC_CTRLB1 | read-write | 0x00000000 |
0x400C4078 | DMAC Channel Configuration Register (ch_num = 1) | DMAC_CFG1 | read-write | 0x01000000 |
0x400C408C | DMAC Channel Source Address Register (ch_num = 2) | DMAC_SADDR2 | read-write | 0x00000000 |
0x400C4090 | DMAC Channel Destination Address Register (ch_num = 2) | DMAC_DADDR2 | read-write | 0x00000000 |
0x400C4094 | DMAC Channel Descriptor Address Register (ch_num = 2) | DMAC_DSCR2 | read-write | 0x00000000 |
0x400C4098 | DMAC Channel Control A Register (ch_num = 2) | DMAC_CTRLA2 | read-write | 0x00000000 |
0x400C409C | DMAC Channel Control B Register (ch_num = 2) | DMAC_CTRLB2 | read-write | 0x00000000 |
0x400C40A0 | DMAC Channel Configuration Register (ch_num = 2) | DMAC_CFG2 | read-write | 0x01000000 |
0x400C40B4 | DMAC Channel Source Address Register (ch_num = 3) | DMAC_SADDR3 | read-write | 0x00000000 |
0x400C40B8 | DMAC Channel Destination Address Register (ch_num = 3) | DMAC_DADDR3 | read-write | 0x00000000 |
0x400C40BC | DMAC Channel Descriptor Address Register (ch_num = 3) | DMAC_DSCR3 | read-write | 0x00000000 |
0x400C40C0 | DMAC Channel Control A Register (ch_num = 3) | DMAC_CTRLA3 | read-write | 0x00000000 |
0x400C40C4 | DMAC Channel Control B Register (ch_num = 3) | DMAC_CTRLB3 | read-write | 0x00000000 |
0x400C40C8 | DMAC Channel Configuration Register (ch_num = 3) | DMAC_CFG3 | read-write | 0x01000000 |
0x400C40DC | DMAC Channel Source Address Register (ch_num = 4) | DMAC_SADDR4 | read-write | 0x00000000 |
0x400C40E0 | DMAC Channel Destination Address Register (ch_num = 4) | DMAC_DADDR4 | read-write | 0x00000000 |
0x400C40E4 | DMAC Channel Descriptor Address Register (ch_num = 4) | DMAC_DSCR4 | read-write | 0x00000000 |
0x400C40E8 | DMAC Channel Control A Register (ch_num = 4) | DMAC_CTRLA4 | read-write | 0x00000000 |
0x400C40EC | DMAC Channel Control B Register (ch_num = 4) | DMAC_CTRLB4 | read-write | 0x00000000 |
0x400C40F0 | DMAC Channel Configuration Register (ch_num = 4) | DMAC_CFG4 | read-write | 0x01000000 |
0x400C4104 | DMAC Channel Source Address Register (ch_num = 5) | DMAC_SADDR5 | read-write | 0x00000000 |
0x400C4108 | DMAC Channel Destination Address Register (ch_num = 5) | DMAC_DADDR5 | read-write | 0x00000000 |
0x400C410C | DMAC Channel Descriptor Address Register (ch_num = 5) | DMAC_DSCR5 | read-write | 0x00000000 |
0x400C4110 | DMAC Channel Control A Register (ch_num = 5) | DMAC_CTRLA5 | read-write | 0x00000000 |
0x400C4114 | DMAC Channel Control B Register (ch_num = 5) | DMAC_CTRLB5 | read-write | 0x00000000 |
0x400C4118 | DMAC Channel Configuration Register (ch_num = 5) | DMAC_CFG5 | read-write | 0x01000000 |
0x400C41E4 | DMAC Write Protect Mode Register | DMAC_WPMR | read-write | 0x00000000 |
0x400C41E8 | DMAC Write Protect Status Register | DMAC_WPSR | read-only | 0x00000000 |
Register Fields
DMAC DMAC Global Configuration Register
Name: DMAC_GCFG
Access: read-write
Address: 0x400C4000
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | ARB_CFG | - | - | - | - |
- ARB_CFG: Arbiter Configuration
Value Name Description 0 FIXED Fixed priority arbiter. 1 ROUND_ROBIN Modified round robin arbiter.
DMAC DMAC Enable Register
Name: DMAC_EN
Access: read-write
Address: 0x400C4004
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | ENABLE |
-
ENABLE
Value Name Description 0 - DMA Controller is disabled. 1 - DMA Controller is enabled.
DMAC DMAC Software Single Request Register
Name: DMAC_SREQ
Access: read-write
Address: 0x400C4008
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DSREQ5 | SSREQ5 | DSREQ4 | SSREQ4 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSREQ3 | SSREQ3 | DSREQ2 | SSREQ2 | DSREQ1 | SSREQ1 | DSREQ0 | SSREQ0 |
- SSREQ0: Source Request
- DSREQ0: Destination Request
- SSREQ1: Source Request
- DSREQ1: Destination Request
- SSREQ2: Source Request
- DSREQ2: Destination Request
- SSREQ3: Source Request
- DSREQ3: Destination Request
- SSREQ4: Source Request
- DSREQ4: Destination Request
- SSREQ5: Source Request
- DSREQ5: Destination Request
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Software Chunk Transfer Request Register
Name: DMAC_CREQ
Access: read-write
Address: 0x400C400C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DCREQ5 | SCREQ5 | DCREQ4 | SCREQ4 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCREQ3 | SCREQ3 | DCREQ2 | SCREQ2 | DCREQ1 | SCREQ1 | DCREQ0 | SCREQ0 |
- SCREQ0: Source Chunk Request
- DCREQ0: Destination Chunk Request
- SCREQ1: Source Chunk Request
- DCREQ1: Destination Chunk Request
- SCREQ2: Source Chunk Request
- DCREQ2: Destination Chunk Request
- SCREQ3: Source Chunk Request
- DCREQ3: Destination Chunk Request
- SCREQ4: Source Chunk Request
- DCREQ4: Destination Chunk Request
- SCREQ5: Source Chunk Request
- DCREQ5: Destination Chunk Request
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Software Last Transfer Flag Register
Name: DMAC_LAST
Access: read-write
Address: 0x400C4010
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | DLAST5 | SLAST5 | DLAST4 | SLAST4 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLAST3 | SLAST3 | DLAST2 | SLAST2 | DLAST1 | SLAST1 | DLAST0 | SLAST0 |
- SLAST0: Source Last
- DLAST0: Destination Last
- SLAST1: Source Last
- DLAST1: Destination Last
- SLAST2: Source Last
- DLAST2: Destination Last
- SLAST3: Source Last
- DLAST3: Destination Last
- SLAST4: Source Last
- DLAST4: Destination Last
- SLAST5: Source Last
- DLAST5: Destination Last
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
Name: DMAC_EBCIER
Access: write-only
Address: 0x400C4018
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | ERR5 | ERR4 | ERR3 | ERR2 | ERR1 | ERR0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | CBTC5 | CBTC4 | CBTC3 | CBTC2 | CBTC1 | CBTC0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | BTC5 | BTC4 | BTC3 | BTC2 | BTC1 | BTC0 |
- BTC0: Buffer Transfer Completed [5:0]
- BTC1: Buffer Transfer Completed [5:0]
- BTC2: Buffer Transfer Completed [5:0]
- BTC3: Buffer Transfer Completed [5:0]
- BTC4: Buffer Transfer Completed [5:0]
- BTC5: Buffer Transfer Completed [5:0]
- CBTC0: Chained Buffer Transfer Completed [5:0]
- CBTC1: Chained Buffer Transfer Completed [5:0]
- CBTC2: Chained Buffer Transfer Completed [5:0]
- CBTC3: Chained Buffer Transfer Completed [5:0]
- CBTC4: Chained Buffer Transfer Completed [5:0]
- CBTC5: Chained Buffer Transfer Completed [5:0]
- ERR0: Access Error [5:0]
- ERR1: Access Error [5:0]
- ERR2: Access Error [5:0]
- ERR3: Access Error [5:0]
- ERR4: Access Error [5:0]
- ERR5: Access Error [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
Name: DMAC_EBCIDR
Access: write-only
Address: 0x400C401C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | ERR5 | ERR4 | ERR3 | ERR2 | ERR1 | ERR0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | CBTC5 | CBTC4 | CBTC3 | CBTC2 | CBTC1 | CBTC0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | BTC5 | BTC4 | BTC3 | BTC2 | BTC1 | BTC0 |
- BTC0: Buffer Transfer Completed [5:0]
- BTC1: Buffer Transfer Completed [5:0]
- BTC2: Buffer Transfer Completed [5:0]
- BTC3: Buffer Transfer Completed [5:0]
- BTC4: Buffer Transfer Completed [5:0]
- BTC5: Buffer Transfer Completed [5:0]
- CBTC0: Chained Buffer Transfer Completed [5:0]
- CBTC1: Chained Buffer Transfer Completed [5:0]
- CBTC2: Chained Buffer Transfer Completed [5:0]
- CBTC3: Chained Buffer Transfer Completed [5:0]
- CBTC4: Chained Buffer Transfer Completed [5:0]
- CBTC5: Chained Buffer Transfer Completed [5:0]
- ERR0: Access Error [5:0]
- ERR1: Access Error [5:0]
- ERR2: Access Error [5:0]
- ERR3: Access Error [5:0]
- ERR4: Access Error [5:0]
- ERR5: Access Error [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
Name: DMAC_EBCIMR
Access: read-only
Address: 0x400C4020
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | ERR5 | ERR4 | ERR3 | ERR2 | ERR1 | ERR0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | CBTC5 | CBTC4 | CBTC3 | CBTC2 | CBTC1 | CBTC0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | BTC5 | BTC4 | BTC3 | BTC2 | BTC1 | BTC0 |
- BTC0: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - BTC1: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - BTC2: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - BTC3: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - BTC4: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - BTC5: Buffer Transfer Completed [5:0]
Value Name Description 0 - Buffer Transfer Completed Interrupt is disabled for channel i. 1 - Buffer Transfer Completed Interrupt is enabled for channel i. - CBTC0: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - CBTC1: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - CBTC2: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - CBTC3: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - CBTC4: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - CBTC5: Chained Buffer Transfer Completed [5:0]
Value Name Description 0 - Chained Buffer Transfer interrupt is disabled for channel i. 1 - Chained Buffer Transfer interrupt is enabled for channel i. - ERR0: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i. - ERR1: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i. - ERR2: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i. - ERR3: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i. - ERR4: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i. - ERR5: Access Error [5:0]
Value Name Description 0 - Transfer Error Interrupt is disabled for channel i. 1 - Transfer Error Interrupt is enabled for channel i.
DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
Name: DMAC_EBCISR
Access: read-only
Address: 0x400C4024
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | ERR5 | ERR4 | ERR3 | ERR2 | ERR1 | ERR0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | CBTC5 | CBTC4 | CBTC3 | CBTC2 | CBTC1 | CBTC0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | BTC5 | BTC4 | BTC3 | BTC2 | BTC1 | BTC0 |
- BTC0: Buffer Transfer Completed [5:0]
- BTC1: Buffer Transfer Completed [5:0]
- BTC2: Buffer Transfer Completed [5:0]
- BTC3: Buffer Transfer Completed [5:0]
- BTC4: Buffer Transfer Completed [5:0]
- BTC5: Buffer Transfer Completed [5:0]
- CBTC0: Chained Buffer Transfer Completed [5:0]
- CBTC1: Chained Buffer Transfer Completed [5:0]
- CBTC2: Chained Buffer Transfer Completed [5:0]
- CBTC3: Chained Buffer Transfer Completed [5:0]
- CBTC4: Chained Buffer Transfer Completed [5:0]
- CBTC5: Chained Buffer Transfer Completed [5:0]
- ERR0: Access Error [5:0]
- ERR1: Access Error [5:0]
- ERR2: Access Error [5:0]
- ERR3: Access Error [5:0]
- ERR4: Access Error [5:0]
- ERR5: Access Error [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Channel Handler Enable Register
Name: DMAC_CHER
Access: write-only
Address: 0x400C4028
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | KEEP5 | KEEP4 | KEEP3 | KEEP2 | KEEP1 | KEEP0 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | SUSP5 | SUSP4 | SUSP3 | SUSP2 | SUSP1 | SUSP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | ENA5 | ENA4 | ENA3 | ENA2 | ENA1 | ENA0 |
- ENA0: Enable [5:0]
- ENA1: Enable [5:0]
- ENA2: Enable [5:0]
- ENA3: Enable [5:0]
- ENA4: Enable [5:0]
- ENA5: Enable [5:0]
- SUSP0: Suspend [5:0]
- SUSP1: Suspend [5:0]
- SUSP2: Suspend [5:0]
- SUSP3: Suspend [5:0]
- SUSP4: Suspend [5:0]
- SUSP5: Suspend [5:0]
- KEEP0: Keep on [5:0]
- KEEP1: Keep on [5:0]
- KEEP2: Keep on [5:0]
- KEEP3: Keep on [5:0]
- KEEP4: Keep on [5:0]
- KEEP5: Keep on [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Channel Handler Disable Register
Name: DMAC_CHDR
Access: write-only
Address: 0x400C402C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | RES5 | RES4 | RES3 | RES2 | RES1 | RES0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | DIS5 | DIS4 | DIS3 | DIS2 | DIS1 | DIS0 |
- DIS0: Disable [5:0]
- DIS1: Disable [5:0]
- DIS2: Disable [5:0]
- DIS3: Disable [5:0]
- DIS4: Disable [5:0]
- DIS5: Disable [5:0]
- RES0: Resume [5:0]
- RES1: Resume [5:0]
- RES2: Resume [5:0]
- RES3: Resume [5:0]
- RES4: Resume [5:0]
- RES5: Resume [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Channel Handler Status Register
Name: DMAC_CHSR
Access: read-only
Address: 0x400C4030
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | STAL5 | STAL4 | STAL3 | STAL2 | STAL1 | STAL0 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | EMPT5 | EMPT4 | EMPT3 | EMPT2 | EMPT1 | EMPT0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | SUSP5 | SUSP4 | SUSP3 | SUSP2 | SUSP1 | SUSP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | ENA5 | ENA4 | ENA3 | ENA2 | ENA1 | ENA0 |
- ENA0: Enable [5:0]
- ENA1: Enable [5:0]
- ENA2: Enable [5:0]
- ENA3: Enable [5:0]
- ENA4: Enable [5:0]
- ENA5: Enable [5:0]
- SUSP0: Suspend [5:0]
- SUSP1: Suspend [5:0]
- SUSP2: Suspend [5:0]
- SUSP3: Suspend [5:0]
- SUSP4: Suspend [5:0]
- SUSP5: Suspend [5:0]
- EMPT0: Empty [5:0]
- EMPT1: Empty [5:0]
- EMPT2: Empty [5:0]
- EMPT3: Empty [5:0]
- EMPT4: Empty [5:0]
- EMPT5: Empty [5:0]
- STAL0: Stalled [5:0]
- STAL1: Stalled [5:0]
- STAL2: Stalled [5:0]
- STAL3: Stalled [5:0]
- STAL4: Stalled [5:0]
- STAL5: Stalled [5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DMAC DMAC Channel Source Address Register (ch_num = 0)
Name: DMAC_SADDR0
Access: read-write
Address: 0x400C403C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
-
DMAC DMAC Channel Destination Address Register (ch_num = 0)
Name: DMAC_DADDR0
Access: read-write
Address: 0x400C4040
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
-
DMAC DMAC Channel Descriptor Address Register (ch_num = 0)
Name: DMAC_DSCR0
Access: read-write
Address: 0x400C4044
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
-
DMAC DMAC Channel Control A Register (ch_num = 0)
Name: DMAC_CTRLA0
Access: read-write
Address: 0x400C4048
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
-
DMAC DMAC Channel Control B Register (ch_num = 0)
Name: DMAC_CTRLB0
Access: read-write
Address: 0x400C404C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
-
DMAC DMAC Channel Configuration Register (ch_num = 0)
Name: DMAC_CFG0
Access: read-write
Address: 0x400C4050
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
-
-
DMAC DMAC Channel Source Address Register (ch_num = 1)
Name: DMAC_SADDR1
Access: read-write
Address: 0x400C4064
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
-
DMAC DMAC Channel Destination Address Register (ch_num = 1)
Name: DMAC_DADDR1
Access: read-write
Address: 0x400C4068
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
-
DMAC DMAC Channel Descriptor Address Register (ch_num = 1)
Name: DMAC_DSCR1
Access: read-write
Address: 0x400C406C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
-
DMAC DMAC Channel Control A Register (ch_num = 1)
Name: DMAC_CTRLA1
Access: read-write
Address: 0x400C4070
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
-
DMAC DMAC Channel Control B Register (ch_num = 1)
Name: DMAC_CTRLB1
Access: read-write
Address: 0x400C4074
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
-
DMAC DMAC Channel Configuration Register (ch_num = 1)
Name: DMAC_CFG1
Access: read-write
Address: 0x400C4078
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
-
-
DMAC DMAC Channel Source Address Register (ch_num = 2)
Name: DMAC_SADDR2
Access: read-write
Address: 0x400C408C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
-
DMAC DMAC Channel Destination Address Register (ch_num = 2)
Name: DMAC_DADDR2
Access: read-write
Address: 0x400C4090
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
-
DMAC DMAC Channel Descriptor Address Register (ch_num = 2)
Name: DMAC_DSCR2
Access: read-write
Address: 0x400C4094
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
-
DMAC DMAC Channel Control A Register (ch_num = 2)
Name: DMAC_CTRLA2
Access: read-write
Address: 0x400C4098
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
-
DMAC DMAC Channel Control B Register (ch_num = 2)
Name: DMAC_CTRLB2
Access: read-write
Address: 0x400C409C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
-
DMAC DMAC Channel Configuration Register (ch_num = 2)
Name: DMAC_CFG2
Access: read-write
Address: 0x400C40A0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
-
-
DMAC DMAC Channel Source Address Register (ch_num = 3)
Name: DMAC_SADDR3
Access: read-write
Address: 0x400C40B4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
-
DMAC DMAC Channel Destination Address Register (ch_num = 3)
Name: DMAC_DADDR3
Access: read-write
Address: 0x400C40B8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
-
DMAC DMAC Channel Descriptor Address Register (ch_num = 3)
Name: DMAC_DSCR3
Access: read-write
Address: 0x400C40BC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
-
DMAC DMAC Channel Control A Register (ch_num = 3)
Name: DMAC_CTRLA3
Access: read-write
Address: 0x400C40C0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
-
DMAC DMAC Channel Control B Register (ch_num = 3)
Name: DMAC_CTRLB3
Access: read-write
Address: 0x400C40C4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
-
DMAC DMAC Channel Configuration Register (ch_num = 3)
Name: DMAC_CFG3
Access: read-write
Address: 0x400C40C8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
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DMAC DMAC Channel Source Address Register (ch_num = 4)
Name: DMAC_SADDR4
Access: read-write
Address: 0x400C40DC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
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DMAC DMAC Channel Destination Address Register (ch_num = 4)
Name: DMAC_DADDR4
Access: read-write
Address: 0x400C40E0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
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DMAC DMAC Channel Descriptor Address Register (ch_num = 4)
Name: DMAC_DSCR4
Access: read-write
Address: 0x400C40E4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
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DMAC DMAC Channel Control A Register (ch_num = 4)
Name: DMAC_CTRLA4
Access: read-write
Address: 0x400C40E8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
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DMAC DMAC Channel Control B Register (ch_num = 4)
Name: DMAC_CTRLB4
Access: read-write
Address: 0x400C40EC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
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DMAC DMAC Channel Configuration Register (ch_num = 4)
Name: DMAC_CFG4
Access: read-write
Address: 0x400C40F0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
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DMAC DMAC Channel Source Address Register (ch_num = 5)
Name: DMAC_SADDR5
Access: read-write
Address: 0x400C4104
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR |
- SADDR: Channel x Source Address
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DMAC DMAC Channel Destination Address Register (ch_num = 5)
Name: DMAC_DADDR5
Access: read-write
Address: 0x400C4108
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DADDR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DADDR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DADDR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DADDR |
- DADDR: Channel x Destination Address
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DMAC DMAC Channel Descriptor Address Register (ch_num = 5)
Name: DMAC_DSCR5
Access: read-write
Address: 0x400C410C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DSCR | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSCR | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSCR | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSCR | - | - |
- DSCR: Buffer Transfer Descriptor Address
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DMAC DMAC Channel Control A Register (ch_num = 5)
Name: DMAC_CTRLA5
Access: read-write
Address: 0x400C4110
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DONE | - | DST_WIDTH | - | - | SRC_WIDTH | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | DCSIZE | - | SCSIZE | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BTSIZE | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTSIZE |
- BTSIZE: Buffer Transfer Size
- SCSIZE: Source Chunk Transfer Size.
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - DCSIZE: Destination Chunk Transfer Size
Value Name Description 0x0 CHK_1 1 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 CHK_32 32 data transferred 0x5 CHK_64 64 data transferred 0x6 CHK_128 128 data transferred 0x7 CHK_256 256 data transferred - SRC_WIDTH: Transfer Width for the Source
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width - DST_WIDTH: Transfer Width for the Destination
Value Name Description 0x0 BYTE the transfer size is set to 8-bit width 0x1 HALF_WORD the transfer size is set to 16-bit width 0x2 WORD the transfer size is set to 32-bit width -
DONE
Value Name Description 0 - The transfer is performed. 1 - If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-tent of this register.
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DMAC DMAC Channel Control B Register (ch_num = 5)
Name: DMAC_CTRLB5
Access: read-write
Address: 0x400C4114
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | IEN | DST_INCR | - | - | SRC_INCR | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FC | DST_DSCR | - | - | - | SRC_DSCR | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | - |
- SRC_DSCR: Source Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. - DST_DSCR: Destination Address Descriptor
Value Name Description 0 FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 1 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. - FC: Flow Control
Value Name Description 0x0 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x1 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x2 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x3 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller - SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value Name Description 0x0 INCREMENTING The source address is incremented 0x1 DECREMENTING The source address is decremented 0x2 FIXED The source address remains unchanged - DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value Name Description 0x0 INCREMENTING The destination address is incremented 0x1 DECREMENTING The destination address is decremented 0x2 FIXED The destination address remains unchanged - IEN
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DMAC DMAC Channel Configuration Register (ch_num = 5)
Name: DMAC_CFG5
Access: read-write
Address: 0x400C4118
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | FIFOCFG | - | AHB_PROT | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | LOCK_IF_L | LOCK_B | LOCK_IF | - | - | - | SOD |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DST_H2SEL | - | - | - | SRC_H2SEL | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DST_PER | SRC_PER |
- SRC_PER: Source with Peripheral identifier
- DST_PER: Destination with Peripheral identifier
- SRC_H2SEL: Software or Hardware Selection for the Source
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - DST_H2SEL: Software or Hardware Selection for the Destination
Value Name Description 0 SW Software handshaking interface is used to trigger a transfer request. 1 HW Hardware handshaking interface is used to trigger a transfer request. - SOD: Stop On Done
Value Name Description 0 DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. - LOCK_IF: Interface Lock
Value Name Description 0 DISABLE Interface Lock capability is disabled 1 ENABLE Interface Lock capability is enabled - LOCK_B: Bus Lock
Value Name Description 0 DISABLE AHB Bus Locking capability is disabled. - LOCK_IF_L: Master Interface Arbiter Lock
Value Name Description 0 CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. - AHB_PROT: AHB Protection
Value Name Description 1 - Data access - FIFOCFG: FIFO Configuration
Value Name Description 0x0 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x1 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x2 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced.
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DMAC DMAC Write Protect Mode Register
Name: DMAC_WPMR
Access: read-write
Address: 0x400C41E4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WPKEY | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPKEY | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPKEY | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPEN |
- WPEN: Write Protect Enable
Value Name Description 0 - Disables the Write Protect if WPKEY corresponds to 0x444D4143 ("DMAC" in ASCII). 1 - Enables the Write Protect if WPKEY corresponds to 0x444D4143 ("DMAC" in ASCII). - WPKEY: Write Protect KEY
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DMAC DMAC Write Protect Status Register
Name: DMAC_WPSR
Access: read-only
Address: 0x400C41E8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPVSRC | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPVSRC | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPVS |
- WPVS: Write Protect Violation Status
Value Name Description 0 - No Write Protect Violation has occurred since the last read of the DMAC_WPSR register. 1 - A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unauthor-ized attempt to write a protected register, the associated violation is reported into field WPVSRC. - WPVSRC: Write Protect Violation Source
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