| Rule Violations |
Count |
| Acute Angle Constraint (Minimum=60.000) (All) |
33 |
| Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=24mil) (Air Gap=10mil) (Entries=4) (InNet('+12V')) |
0 |
| Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (IsVia) |
0 |
| Clearance Constraint (Gap=7mil) (IsVia),(IsVia) |
0 |
| Clearance Constraint (Gap=7mil) (IsPad),(IsVia) |
0 |
| Clearance Constraint (Gap=7mil) (IsPad),(IsPad) |
0 |
| Clearance Constraint (Gap=7mil) ((InLayerClass('Signal Layers') AND IsTrack)),(IsVia) |
0 |
| Clearance Constraint (Gap=7mil) ((InLayerClass('Signal Layers') AND IsTrack)),(IsPad) |
0 |
| Clearance Constraint (Gap=7mil) ((InLayerClass('Signal Layers') AND IsTrack)),((InLayerClass('Signal Layers') AND IsTrack)) |
0 |
| Net Antennae (Tolerance=0mil) (All) |
0 |
| Silk primitive without silk layer |
4 |
| Silk to Silk (Clearance=10mil) (Disabled)(All),(All) |
0 |
| Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=4mil) (All),(All) |
0 |
| Hole To Hole Clearance (Gap=8mil) (All),(All) |
0 |
| Hole Size Constraint (Min=15mil) (Max=100000mil) (All) |
0 |
| Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) |
0 |
| Width Constraint (Min=7mil) (Max=250mil) (Preferred=24mil) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) |
0 |
| Clearance Constraint (Gap=7mil) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| SMD To Corner (Distance=3mil) (All) |
21 |
| Minimum Annular Ring (Minimum=7mil) (All) |
0 |
| Total |
58 |
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